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ES4428 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers |
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ES4428 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers |
3 / 10 page 3 SAM0358-052201 ESS Technology, Inc. ES4428/ES4427 PRODUCT BRIEF ES4428 PIN DESCRIPTION Table 1 lists the pin descriptions for the ES4428. Table 1 ES4428 Pin Descriptions Name Number I/O Definition VCC 1, 9, 18, 27, 35, 44, 51, 59, 68, 75, 83, 92, 99, 104, 111, 121, 130, 139, 148, 157, 164, 172, 183, 193, 201 I 3.3V power supply. VSS 8, 17, 26, 34, 43, 52, 60, 67, 76, 84, 91, 98, 103, 112, 120, 129, 138, 147, 156, 163, 171, 177, 184, 192, 200, 208 I Ground. LA[21:0] 23:19,16:10,7:2,207:204 O Device address output. RESET# 24 I Reset. TDMDX 25 O TDM transmit data output. RSEL I ROM Select. TDMDR 28 I TDM receive data input. TDMCLK 29 I TDM clock input. TDMFS 30 I TDM frame sync. TDMTSC# 31 O TDM output enable. TWS 32 O Audio transmit frame sync output. SEL_PLL1 System and DSCK output clock frequency selection at reset time. The matrix below lists the available clock frequencies and their respective PLL bit settings.. TSD 33 O Audio transmit serial data output. SEL_PLL0 I Refer to the description and matrix for SEL_PLL1 pin 32. SEL_PLL2 36 I Refer to the description and matrix for SEL_PLL1 pin 32. NC 37, 38, 41, 42, 146:142, 155:149, 158, 203:202 — No connect. Leave open. MCLK 39 I/O Audio master clock for audio DAC. TBCK 40 I/O Audio transmit bit clock output. RSD 45 I Audio receive serial data input. RWS 46 I Audio receive frame sync input. RBCK 47 I Audio receive bit clock input. APLLCAP 48 I Analog PLL capacitor input. RSEL Selection 0 16-bit ROM 1 8-bit ROM SEL_PLL2 SEL_PLL1 SEL_PLL0 Clock Output 0 0 0 VCO doesn’t work. 00 1 27 MHz 0 1 0 Bypass mode 01 1 54 MHz 1 0 0 121.5 MHz 10 1 81 MHz 1 1 0 94.5 MHz 1 1 1 108 MHz |
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