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AD677KN Datasheet(PDF) 5 Page - Analog Devices |
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AD677KN Datasheet(HTML) 5 Page - Analog Devices |
5 / 17 page AD677 REV. A –4– (TMIN to TMAX, VCC = +12 V 5%, VEE = –12 V 5%, VDD = +5 V 10%) 1 TIMING SPECIFICATIONS Parameter Symbol Min Typ Max Units Conversion Period 2, 3 tC 10 1000 µs CLK Period 4 tCLK 480 ns Calibration Time tCT 85532 tCLK Sampling Time tS 2 µs Last CLK to SAMPLE Delay 5 tLCS 2.1 µs SAMPLE Low tSL 100 ns SAMPLE to Busy Delay tSS 30 75 ns 1st CLK Delay tFCD 50 ns CLK Low 6 tCL 50 ns CLK High 6 tCH 50 ns CLK to BUSY Delay tCB 180 300 ns CLK to SDATA Valid tCD 50 100 175 ns CLK to SCLK High tCSH 100 180 300 ns SCLK Low tSCL 50 80 ns SDATA to SCLK High tDSH 50 80 ns CAL High Time tCALH 50 ns CAL to BUSY Delay tCALB 15 50 ns NOTES 1See the “CONVERSION CONTROL” and “AUTOCALIBRATION” sections for detailed explanations of the above timing. 2Depends upon external clock frequency; includes acquisition time and conversion time. The maximum conversion period is specified to account for the droop of the internal sample/hold function. Operation at slower rates may degrade performance. 3t C = tFCD + 16 × t CLK + tLCS. 4580 ns is recommended for optimal accuracy over temperature (not necessary during calibration cycle). 5If SAMPLE goes high before the 17th CLK pulse, the device will start sampling approximately 100 ns after the rising edge of the 17th CLK pulse. 6t CH + tCL = tCLK and must be greater than 480 ns. CAL (INPUT) BUSY (OUTPUT) CLK * (INPUT) t CT t CALH t CALB t CB t FCD 85530 85531 85532 1 23 t CL t CH t CLK *SHADED PORTIONS OF INPUT SIGNALS ARE OPTIONAL. FOR BEST PERFORMANCE, WE RECOMMEND THAT THESE SIGNALS BE HELD LOW EXCEPT WHEN EXPLICITY SHOWN HIGH. Figure 1. Calibration Timing t CB BUSY (OUTPUT) t FCD t CH *SHADED PORTIONS OF INPUT SIGNALS ARE OPTIONAL. FOR BEST PERFORMANCE, WE RECOMMEND THAT THESE SIGNALS BE HELD LOW EXCEPT WHEN EXPLICITY SHOWN HIGH. SAMPLE* (INPUT) t S CLK * (INPUT) 1 23 15 16 17 t S t LCS MSB BIT 2 BIT 15 BIT 13 BIT 14 BIT 16 SCLK (OUTPUT) SDATA (OUTPUT) OLD BIT 16 t C t CD t SCL t DSH t SB t SL t CLK t CSH t CL Figure 2. General Conversion Timing |
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