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LM76002-Q1 Datasheet(PDF) 19 Page - Texas Instruments

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No. de pieza LM76002-Q1
Descripción Electrónicos  3.5-V to 60-V, 2.5-A/3.5-A Synchronous Step-Down Voltage Regulator
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

LM76002-Q1 Datasheet(HTML) 19 Page - Texas Instruments

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RTERM
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19
LM76002-Q1, LM76003-Q1
www.ti.com
SNVSAU3 – DECEMBER 2017
Product Folder Links: LM76002-Q1 LM76003-Q1
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Copyright © 2017, Texas Instruments Incorporated
The LM76002-Q1/LM76003-Q1 switching action can also be synchronized to an external clock from 300 kHz to
2.2 MHz. TI recommends connecting an external clock to the SYNC pin with appropriate termination resistor.
Ground the SYNC pin if not used.
Figure 18. Frequency Synchronization
The recommendations for the external clock include high level no lower than 2 V, low level no higher than 0.4 V,
duty cycle between 10% and 90%, and both positive and negative pulse width no shorter than 80 ns. When the
external clock fails at logic high or low, the LM76002-Q1/LM76003-Q1 switches at the frequency programmed by
the RT resistor after a time-out period. TI recommends connecting a resistor RT to the RT pin so that the internal
oscillator frequency is the same as the target clock frequency when the LM76002-Q1/LM76003-Q1 is
synchronized to an external clock. This allows the regulator to continue operating at approximately the same
switching frequency if the external clock fails.
The choice of switching frequency is usually a compromise between conversion efficiency and the size of the
circuit. Lower switching frequency implies reduced switching losses (including gate charge losses, switch
transition losses, etc.) and usually results in higher overall efficiency. However, higher switching frequency allows
use of smaller LC output filters and hence a more compact design. Lower inductance also helps transient
response (higher large signal slew rate of inductor current), and reduces the DCR loss. The optimal switching
frequency is usually a trade-off in a given application and thus needs to be determined on a case-by-case basis.
It is related to the input voltage, output voltage, most frequent load current level(s), external component choices,
and circuit size requirement. The choice of switching frequency may also be limited if an operating condition
triggers tON-MIN or tOFF-MIN.
7.3.8 Minimum On-Time, Minimum Off-Time, and Frequency Foldback at Dropout Conditions
Minimum on-time, tON-MIN, is the smallest duration of time that the HS switch can be on. tON-MIN is typically 65 ns
in the LM76002-Q1/LM76003-Q1. Minimum off-time, tOFF-MIN, is the smallest duration that the HS switch can be
off. tOFF-MIN is typically 95 ns in the LM76002-Q1/LM76003-Q1. In CCM operation, tON-MIN and tOFF-MIN limits the
voltage conversion range given a selected switching frequency. The minimum duty cycle allowed is:
DMIN = tON-MIN × fSW
(7)
And the maximum duty cycle allowed is:
DMAX = 1 – tOFF-MIN × fSW
(8)
Given fixed tON-MIN and tOFF-MIN, the higher the switching frequency the narrower the range of the allowed duty
cycle. In the LM76002-Q1/LM76003-Q1, frequency foldback scheme is employed to extend the maximum duty
cycle when tOFF-MIN is reached. The switching frequency decreases once longer duty cycle is needed under low
VIN conditions. The switching frequency can be decreased to approximately 1/10 of the programmed frequency
by RT or the synchronization clock. Such a wide range of frequency foldback allows the LM76002-Q1/LM76003-
Q1 output voltage to stay in regulation with a much lower supply voltage VIN. This leads to a lower effective
dropout voltage. See Typical Characteristics for more details.
Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution
size and efficiency. The maximum operational supply voltage can be found by:
VIN_MAX = VOUT / (fSW × tON-MIN)
(9)
At lower supply voltage, the switching frequency decreases once tOFF-MIN is tripped. The minimum VIN without
frequency foldback can be approximated by:
VIN_MIN = VOUT / (fSW × tOFF-MIN)
(10)
Considering power losses in the system with heavy load operation, VIN-MIN is higher than the result calculated in
Equation 10. With frequency foldback, VIN-MIN is lowered by decreased fSW. When the device is operating in auto
mode at voltages near maximum rated input voltage and light load conditions, an increased output voltage ripple
during load transient may be observed. For this reason TI recommends that device operating point be calculated
with sufficient operational margin so that minimum on-time condition is not triggered.


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