CDC960

200MHz CLOCK SYNTHESIZER/DRIVER

WITH SPREAD SPECTRUM CAPABILITY AND DEVICE CONTROL INTERFACE

SCAS675 – APRIL 2002

9

POST OFFICE BOX 655303

SMBus serial interface (continued)

reading the SMBus interface, using address pre-phase

1.

2.

Send dummy byte as command code and validate the acknowledge from the slave.

3.

4.

The slave returns the number of bytes it is going to send (byte count) and validates the acknowledge from

the master.

5.

Read back the desired data bytes and validate the acknowledge sent by the master for each data byte.

Clock

Generator

Addr

(7 bits)

ACK

+8 bits

dummy

ACK

Repeated

Clock

Generator

Addr

(7 bits)

ACK

+8 bit byte

ACK by

Data

ACK by

Data

ACK by

A(6:0)&

R/W

ACK

dummy

command

code

ACK

Re eated

Start

A(6:0)&

R/W

ACK

+8 bit byte

count

ACK by

master

Data

byte 0

ACK by

master

Data

byte N

ACK by

master

D2(H)

D3(H)

reading the SMBus interface, using direct read

1.

2.

The slave returns the number of bytes it is going to send (byte count) and validates the acknowledge from

the master.

3.

Read back the desired data bytes and validate the acknowledge sent by the master for each data byte.

Clock

Generator

Addr (7 bits)

ACK

+8 bit byte

count

ACK by master

Data byte 0

ACK by master

Data byte N

ACK by master

A(6:0)& R/W

ACK

count

ACK by master

Data byte 0

ACK by master

Data byte N

ACK by master

D3(H)