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SLG46127 Datasheet(PDF) 41 Page - Dialog Semiconductor |
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SLG46127 Datasheet(HTML) 41 Page - Dialog Semiconductor |
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41 / 88 page  000-0046127-101 Page 40 of 87 SLG46127 11.0 Analog Comparators (ACMP) There are two Analog Comparator (ACMP) macro cells in the SLG46127. In order for the ACMP cells to be used in a GreenPAK design, the power up signals (ACMP0_pdb and ACMP1_pdb) need to be active. By connecting to signals coming from the Connection Matrix, it is possible to have each ACMP be on continuously, off continuously, or switched on periodically based on a digital signal coming from the Connection Matrix. When ACMP is powered down, output is low. Each of the ACMP cells has a positive input signal that can be provided by a variety of external sources, and can also have a selectable gain stage before connection to the analog comparator. Each of the ACMP cells has a negative input signal that is either created from an internal VREF or provided by way of the external sources. Each of the ACMP cells has a selection for the bandwidth of the input signal, which can be used to save power when low bandwidth signals are input into the analog comparator. And if input frequency > 200 kHz, the output will retain its previous value. Each cell also has a hysteresis selection, to offer hysteresis of 0 mV, 25 mV, 50 mV or 200 mV. During powerup, the ACMP output will remain low, and then become valid 110 µs (max) after POR signal goes high, see Figure 16. Note: Regulator and Charge Pump set to automatic ON/OFF. Each of the ACMP cells has a positive input signal that can be provided by a variety of external sources, and can also have a selectable gain stage (1X, 0.5X, 0.33X, 0.25X) before connection to the analog comparator. The Gain divider is unbuffered and consists of 250 KΩ (typ.) resistors, see Table 33. For gain divider accuracy refer to Table 34. IN- voltage range: 0 - 1.2 V. Can use Vref selection VDD/4 and VDD/3 to maintain this input range. Figure 16. Maximum Power On Delay vs. VDD. Table 33. Gain Divider Input Resistance (typ). Gain 1X 0.5X 0.33X 0.25X Input Resistance 100M 1M 0.75M 1M Table 34. Gain Divider Accuracy. Gain 0.5X 0.33X 0.25X Accuracy ±0.6% ±0.9% ±2.8% 1 2 3 4 5 6 7 8 9 10 11 12 0 10 20 30 40 50 60 70 80 90 00 10 20 VDD (V) -40 roo +85 0 C om 5 C |
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