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SLG46200 Datasheet(PDF) 35 Page - Dialog Semiconductor |
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SLG46200 Datasheet(HTML) 35 Page - Dialog Semiconductor |
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35 / 69 page  000-0046200-124 Page 30 of 64 SLG46200 12.9 ACMP Hysteresis Both ACMP’s have a 50mV hysteresis feature, where either the addition or subtraction of 25mV to the IN- signal will change the ACMP’s output value. The 50mV hysteresis signals are controlled as follows: ACMP0_hy_en, reg<369> when set to “1” will turn on the hysteresis, • Output from “0” becomes “1” when IN+ ≥ IN- + 0.025V • Output from “1” becomes “0” when IN+ ≤ IN- - 0.025V ACMP1_hy_en, reg<370> when set to “1” will turn on the hysteresis, • Output from “0” becomes “1” when IN+ ≥ IN- + 0.025V • Output from “1” becomes “0” when IN+ ≤ IN- - 0.025V 12.10 ACMP0 & ACMP1 Register Settings 12.10.1 ACMP0 Register Settings Table 12. ACMP0 Register Settings Signal Name Signal Function Register Bit Address Register Definition ACMP0_l1u_en ACMP0 1 μA input current option <346> 0: Disable 1: Enable ACMP0_low_bw ACMP0 low bandwidth enable <347> 0: Disable 1: Enable ACMP0_PGA_en PGA gain to ACMP0 input enable <357> 0: Disable (IN+ input from PIN 4) 1: Enable (IN+ input from ADC PGA Out) ACMP0_Vref_sel ACMP0 IN- voltage select <361:358> 0000: 50mV 1000: 600mV 0001: 100mV 1001: 700mV 0010: 150mV 1010: 800mV 0011: 200mV 1011: 900mV 0100: 250mV 1100: 1100mV 0101: 300mV 1101: 1300mV 0110: 400mV 1110: 1500mV 0111: 500mV 1111: External (PIN 8) ACMP0_hy_en ACMP0 50mV hysteresis enable <369> 0: Disable 1: Enable |
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