TPS5615, TPS5618, TPS5625, TPS5633

SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER

SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000

4

POST OFFICE BOX 655303

detailed description

Vref

The reference voltage section consists of a temperature-compensated bandgap reference and a resistive

divider that sets the output voltage option. The output voltage, VREF, is within 1% of the nominal setting over

the full junction temperature range of 0

output of the reference network is indirectly brought out through a buffer to the VREFB pin. The voltage on this

pin will be within 2% of VREF. It is not recommended to drive loads with VREFB, other than setting the hysteresis

of the hysteretic comparator, because the current drawn from VREFB sets the charging current for the slowstart

capacitor. Refer to the

slowstart section for additional information.

hysteretic comparator

The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is

set by 2 external resistors and is centered on VREF. The 2 external resistors form a resistor divider from VREFB

to ANAGND, with the output voltage connecting to the VHYST pin. The hysteresis of the propagation delay from

the comparator inputs to the driver outputs is 250 ns (maximum). The maximum hysteresis setting is 60 mV.

R1

+

R2

V

H

2

VREFB–V

H

Where

VH = desired hysteresis voltage

IO(MAX) = 0.5 µA

VHYST

TPS56xx

VREFB

R1

R2

+ 2

VREFB

* V

H

Figure 1. Setting the Hysteresis Voltage

low-side driver

A, source or sink. The bias to the low-side driver is internally connected to the DRV regulator.

high-side driver

A, source or sink. The high-side driver can be configured either as a ground-referenced driver or as a floating

bootstrap driver. When configured as a floating driver, the bias voltage to the driver is developed from the DRV

regulator. The internal bootstrap diode, connected between the DRV and BOOT pins, is a Schottky for improved

drive efficiency. The maximum voltage that can be applied between BOOT and DRVGND is 30 V. The driver

deadtime control

Deadtime control prevents shoot-through current from flowing through the main power FETs during switching

transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side driver is not allowed

to turn on until the gate-drive voltage to the low-side FET is below 2 V; the low-side driver is not allowed to turn

on until the voltage at the junction of the 2 FETs (Vphase) is below 2 V.