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VSC8113QB Datasheet(PDF) 5 Page - Vitesse Semiconductor Corporation

No. de Pieza. VSC8113QB
Descripción  ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
Descarga  28 Pages
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Fabricante  VITESSE [Vitesse Semiconductor Corporation]
Página de inicio  http://www.vitesse.com
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VSC8113QB Datasheet(HTML) 5 Page - Vitesse Semiconductor Corporation

 
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G52154-0, Rev 4.2
© VITESSE SEMICONDUCTOR CORPORATION
Page 5
3/19/99
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8113
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Figure 3: Facility Loopback Data Path
Equipment Loopback
The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is
set high, the Equipment Loopback mode is activated and the high speed transmit data generated from the paral-
lel to serial conversion of the low speed data (TXIN[7:0]) is selected and converted back to parallel data in the
receiver section and presented at the low speed parallel outputs (RXOUT[7:0]). See Figure 4. The internally
generated 155/622MHz clock is used to generate the low speed receive clock output (RXLSCKOUT). In Equip-
ment Loopback mode the transmit data (TXIN[7:0]) is serialized and presented at the high speed output
(TXDATAOUT) along with the high speed transmit clock (TXCLKOUT) which is generated by the on-chip
clock multiplier unit.
CRU Equipment Loopback
Exactly the same as equipment loopback, the point where the transmit data is looped back is moved all the
way back to the high speed I/O. When the CRUEQLP signal is set high, transmit data is looped back to the
CRU, replacing RXDATAIN±
Figure 4: Equipment Loopback Data Path
D
Q
D
Q
1:8
Serial to
Parallel
Q
D
RXDATAIN
TXDATAOUT
RXOUT[7:0]
Q
D
TXIN[7:0]
8:1
Parallel to
Serial
PLL
0
1
0
1
CRU
TXCLKOUT
FACLOOP
RXCLKIN
0
1
Recovered
Clock
D Q
D
Q
1:8
Serial to
Parallel
Q
D
RXDATAIN
TXDATAOUT
RXOUT[7:0]
Q
D
8:1
Parallel to
Serial
TXIN[7:0]
÷ 8
PLL
÷ 8
RXLSCKOUT
TXLSCKIN
TXLSCKOUT
TXCLKOUT
0
1
EQULOOP


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