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VSC8113QB Datasheet(PDF) 6 Page - Vitesse Semiconductor Corporation

No. de Pieza. VSC8113QB
Descripción  ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
Descarga  28 Pages
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Fabricante  VITESSE [Vitesse Semiconductor Corporation]
Página de inicio  http://www.vitesse.com
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VSC8113QB Datasheet(HTML) 6 Page - Vitesse Semiconductor Corporation

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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8113
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Page 6
© VITESSE SEMICONDUCTOR CORPORATION
G52154-0, Rev 4.2
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
3/19/99
Split Loopback
Equipment and facility loopback modes can be enabled simultaneously. In this case, high-speed serial data
received (RXDATAIN) and received/recovered clock are mux’d through to the high-speed serial outputs
(TXDATAOUT) and (TXCLKOUT). The low-speed transmit byte wide bus(TXIN[7:0]) and (TXLSCKIN) are
mux’d into the low-speed byte wide receive output bus (RXOUT[7:0]) and (RXLSCKOUT). See Figure 5.
Figure 5: Split Loopback Datapath
Loop Timing
LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted high. In this mode the CMU
is bypassed by using the receive clock (RXCLKIN), and the entire part is synchronously clocked from a single
external source.
LOOPTIM1 mode bypasses the REFCLK input and uses the divide-by-8 version of the receive clock as the
reference input to the CMU. This mode is selected by asserting the LOOPTIM1 input high. The part is forced
out of this mode if it is in the Loss of Signal state or in Equipment Loopback to prevent the CMU from feeding
its own clock back.
Clock Synthesis
The VSC8113 uses an integrated phase-locked loop (PLL) for clock synthesis of the 622MHz high speed
clock used for serialization in the transmitter section. The PLL is comprised of a phase-frequency detector
(PFD), an integrating operation amplifier and a voltage controlled oscillator (VCO) configured in classic feed-
back system. The PFD compares the selected divided down version of the 622MHz VCO (select pins B0-B2
select divide-by ratios of 8, 12, 16 and 32, see Table 12) and the reference clock. The integrator provides a trans-
fer function between input phase error and output voltage control. The VCO portion of the PLL is a voltage con-
trolled ring-oscillator with a center frequency of 622MHz.
The reactive elements of the integrator are located off-chip and are connected to the feedback loop of the
amplifier through the CP1, CP2, CN1 and CN2 pins. The configuration of these external surface mounted
capacitors is shown in Figure 6. Table 1 shows the recommended external capacitor values for the configurable
reference frequencies.
D
Q
D
Q
1:8
Serial to
Parallel
Q
D
RXDATAIN
TXDATAOUT
RXOUT[7:0]
Q
D
8:1
Parallel to
Serial
TXIN[[7:0]
0
1
CRU
RXCLKIN
TXCLKOUT
TXLSCKIN
RXLSCKOUT
DSBLCRU
Recovered
Clock


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