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TC35274 Datasheet(PDF) 5 Page - Toshiba Semiconductor |
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TC35274 Datasheet(HTML) 5 Page - Toshiba Semiconductor |
5 / 13 page MPEG-4 Video Decoder LSI Preliminary TC35274 TOSHIBA Confidential 2000-4-27 5/13 Version 0.90 Table 1. System Control Signals Signal Name In/Out Bit Width Description /RESET In 1 System Reset Input (Low Active). When the LSI is reset, this terminal has to be low for more than 16 clock cycles. When power on, the LSI has to be reset after PLL locked. It takes approximately 100us until the PLL locked. STANDBY In 1 System Standby Input (High Active). Stop clock distribution to the LSI. After standby, system reset is required. “0” : Active. “1” : Standby. Table 2. PLL Control Signals Signal Name In/Out Bit Width Description PLLFN In 1 Reference Clock Input. It has to be 13.00MHz to 20MHz with +/- 10% duty. PLLDIV[2:0] In 3 System clock frequency select. System Clock = PLLFN * N. “00” : N=1.0. “01” : N=1.5. “10” : N=2.0 “11” : N=2.5. PLLAVD In 1 Analog PLL Power(VDD). PLLAVS In 1 Analog PLL Ground(VSS). Table 3. Host Interface Signal Name In/Out Bit Width Description /HCS In 1 Chip enable input ( low active). “0” : Chip select. “1” : Non operation. /HWR In 1 Write strobe (low active). “0” : Write operation. “1” : Non operation. /HRD In 1 Read Strobe (low active). “0” : Read operation. “1” : Non operation. HADDR[6:0] In 7 Address signal. HDAT[15:0] In/Out 16 Data signal. HWAIT Out 1 Bus wait signal (low active). “0” : Wait. “1” : Non wait. HINT Out 1 Interrupt signal (high active). “0” : Non operation. “1” : Interrupt Operation. Table 4 Video Display Interface Signal Name In/Out Bit Width Description DISPCLK In 1 Clock signal from display. /DISPHSYNC In 1 HSYNC signal from display. /DISPVSYNC In 1 VSYNC signal form display. /DISPBLK Out 1 Blanking signal to display. DISPPIXEL Out 8 Luminance (Y) and chrominance (Cb,Cr) signal output. |
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Descripción similar - TC35274 |
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