Motor de Búsqueda de Datasheet de Componentes Electrónicos
Selected language     Spanish  ▼
Nombre de pieza
         Descripción


LMZM23600 Datasheet(Hoja de datos) 11 Page - TI store

Click here to check the latest version.
No. de Pieza. LMZM23600
Descripción  36-V, 0.5-A Step-Down DC-DC Power Module in 3.8-mm x 3-mm Package
Descarga  36 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricante  TI1 [TI store]
Página de inicio  http://www.ti.com
Logo 

 11 page
background image
11
LMZM23600
www.ti.com
SNVSB53 – FEBRUARY 2018
Product Folder Links: LMZM23600
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Feature Description (continued)
The control architecture also uses frequency foldback at low input voltage in order to achieve low dropout
voltage, maintaining output regulation as the input voltage falls close to output voltage. The frequency foldback at
low input voltage is active for the ADJ as well as the 5-V and 3.3-V output options. The reduction in frequency is
smooth and continuous and is activated as the off-time approaches the minimum value. Under these conditions,
the LMZM23600 device operates much like a constant off-time converter allowing the maximum duty cycle to
reach 97%. This feature allows output voltage regulation with very low dropout.
The LMZM23600 features exceptional conversion efficiency at light load. As the load current is reduced, the
LMZM23600 transitions to light-load mode if the MODE/SYNC terminal is pulled low. In light-load mode the
device uses diode emulation to reduce the RMS inductor current and the switching frequency is reduced. The
fixed voltage versions (3.3-V and 5-V) do not need an external voltage divider connected to FB, which results in
saving two components and lower standby current when the load is in standby. As a result, the consumed supply
current is only 21 µA (typical) with 24-V to 3.3-V conversion and 24 µA (typical) with 24-V to 5-V conversion,
while the output is regulated with no load.
8.3.2 Soft-Start Function
The LMZM23600 features an internally programmed soft-start time. The soft-start time is fixed internally at about
4 ms and is achieved by ramping the internal reference. The device starts up properly even if there is a voltage
present on output before the activation of the LMZM23600. In such cases, there is no switching until the output
voltage value programmed by the ramping reference voltage is above the pre-biased output value. Once the pre-
biased voltage level is reached by the reference ramp, the switching starts, and the output ramps up smoothly
from the pre-biased value up to the final output voltage.
8.3.3 Enable and External UVLO Function
Some applications may require a precision enable or custom input voltage lock-out (UVLO) functionality. Setting
up external UVLO based on the application needs would prevent the converter from trying to regulate the output
voltage until after the input voltage has reached a desired minimum level. Such function can be used to lower the
current demand from the input supply as the supply is still starting up.
The LMZM23600 features a precision enable (EN) input terminal. The EN input logic has two internal thresholds.
The first rising threshold is at 0.9V typical. Its purpose is to wake up the internal VCC regulator to bias the
internal circuitry. The EN rising threshold to start switching is 1.8V (typical) with 0.5V (typical) hysteresis. A
voltage divider from VIN to EN can be used to set the VIN voltage at which the regulator starts the voltage
conversion. The EN terminal is rated for up to the input voltage and can be connected directly to VIN for an
always-on operation. Pulling the EN pin below 0.4 V puts the LMZM23600 in shutdown mode. In shutdown mode
and 12-V input voltage the LMZM23600 only consumes 1.8 µA (typical) of input current.
8.3.4 Current Limit
The LMZM23600 devices features two current limits inside the IC. A coarse high side or peak current limit is
provided to protect against faults. The high-side current limit limits the duration of the on-period of the high-side
power MOSFET during a given clock cycle. A precision cycle-by-cycle valley current limit prevents excessive
average output current. A new switching cycle is not initiated until the inductor current drops below the valley
current limit.




Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36 


Datasheet Download




Enlace URL

¿ALLDATASHEET es útil para Ud.?  [ DONATE ]  

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Favorito   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl