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CY7C1460KV25 Datasheet(PDF) 24 Page - Cypress Semiconductor |
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CY7C1460KV25 Datasheet(HTML) 24 Page - Cypress Semiconductor |
24 / 32 page Document Number: 001-66679 Rev. *J Page 24 of 32 CY7C1460KV25/CY7C1462KV25 CY7C1460KVE25/CY7C1462KVE25 Switching Characteristics Over the Operating Range Parameter [19, 20] Description –250 –200 –167 Unit Min Max Min Max Min Max tPower[21] VCC (typical) to the first access read or write 1 – 1 – 1 – ms Clock tCYC Clock cycle time 4.0 – 5.0 – 6.0 – ns FMAX Maximum operating frequency – 250 – 200 – 167 MHz tCH Clock HIGH 1.5 – 2.0 – 2.4 – ns tCL Clock LOW 1.5 – 2.0 – 2.4 – ns Output Times tCO Data output valid after CLK rise – 2.5 – 3.2 – 3.4 ns tEOV OE LOW to output valid – 2.6 – 3.0 – 3.4 ns tDOH Data output hold after CLK rise 1.0 – 1.5 – 1.5 – ns tCHZ Clock to high Z [22, 23, 24] – 2.6 – 3.0 – 3.4 ns tCLZ Clock to low Z [22, 23, 24] 1.0 – 1.3 – 1.5 – ns tEOHZ OE HIGH to output high Z [22, 23, 24] – 2.6 – 3.0 – 3.4 ns tEOLZ OE LOW to output low Z [22, 23, 24] 0 – 0 – 0 – ns Set-up Times tAS Address set-up before CLK rise 1.2 – 1.4 – 1.5 – ns tDS Data input set-up before CLK rise 1.2 – 1.4 – 1.5 – ns tCENS CEN set-up before CLK rise 1.2 – 1.4 – 1.5 – ns tWES WE, BWx set-up before CLK rise 1.2 – 1.4 – 1.5 – ns tALS ADV/LD set-up before CLK rise 1.2 – 1.4 – 1.5 – ns tCES Chip select set-up 1.2 – 1.4 – 1.5 – ns Hold Times tAH Address hold after CLK rise 0.3 – 0.4 – 0.5 – ns tDH Data input hold after CLK rise 0.3 – 0.4 – 0.5 – ns tCENH CEN hold after CLK rise 0.3 – 0.4 – 0.5 – ns tWEH WE, BWx hold after CLK rise 0.3 – 0.4 – 0.5 – ns tALH ADV/LD hold after CLK rise 0.3 – 0.4 – 0.5 – ns tCEH Chip select hold after CLK rise 0.3 – 0.4 – 0.5 – ns Notes 19. Timing reference is 1.25 V when VDDQ = 2.5 V. 20. Test conditions shown in (a) of AC Test Loads unless otherwise noted. 21. This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a read or write operation can be initiated. 22. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of Figure 3 on page 23. Transition is measured ± 200 mV from steady-state voltage. 23. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z prior to low Z under the same system conditions. 24. This parameter is sampled and not 100% tested. |
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