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CY7C1541KV18 Datasheet(PDF) 27 Page - Cypress Semiconductor |
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CY7C1541KV18 Datasheet(HTML) 27 Page - Cypress Semiconductor |
27 / 27 page Document Number: 001-15700 Rev. *F Revised July 31, 2009 Page 27 of 27 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. CY7C1541KV18, CY7C1556KV18 CY7C1543KV18, CY7C1545KV18 © Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC psoc.cypress.com Clocks & Buffers clocks.cypress.com Wireless wireless.cypress.com Memories memory.cypress.com Image Sensors image.cypress.com Document History Page Document Title: CY7C1541KV18/CY7C1556KV18/CY7C1543KV18/CY7C1545KV18, 72-Mbit QDR®II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Document Number: 001-15700 Rev. ECN Submission Date Orig. of Change Description of Change ** 1103943 See ECN NXR New datasheet *A 1246904 See ECN VKN/AESA Removed 300 MHz speed bin Added footnote# 2 *B 1739283 See ECN VKN/AESA Converted from Advance Information to Preliminary *C 1922548 See ECN VKN/AESA Corrected typo in the tCYC(min) and tKHKH(min) spec for 333 MHz speed bin Added footnote # 22 related to IDD Changed PLL lock time from 2048 cycles to 20 μs Corrected typo in footnote # 26 *D 2612383 11/25/08 VKN/AESA Changed JTAG ID [31:29] from 001 to 000, Updated Power up sequence waveform and it’s description, Included Thermal Resistance values, Changed the package size from 15 x 17 x 1.4 mm to 13 x 15 x 1.4 mm. Updated data sheet template. *E 2697841 04/24/09 VKN Moved to external web *F 2746858 07/31/09 VKN Converted from preliminary to final For 450 MHz speed, changed tCO, tCCQO, tCHZ from 370 ps to 450 ps and tDOH, tCQOH, tCLZ from -370 ps to -450 ps Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information [+] Feedback |
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