SMM205

Preliminary Information

Summit Microelectronics, Inc

2069 1.4 6/23/03

4

PIN DESCRIPTIONS

Pin

Number

Pin

Type

Pin Name

Pin Description

28

DATA

SDA

I

1

CLK

SCL

I

2

I

A2

4

I

A1

6

I

A0

The address pins are biased either to VDD_CAP or GND. When

communicating with the SMM205 over the 2-wire bus these pins provide a

mechanism for assigning a unique bus address.

8

I

WP#

Write Protect active low input. When asserted writes to the configuration

registers and general purpose EE are not allowed.

10

CAP

FILT_CAP

External capacitor input used to filter the VM inputs.

15, 18

CAP

TRIM_CAPx

External capacitor input used for Active Control and margining.

16, 20

O

TRIMx

Output voltage used to control and/or margin converter voltages. Connect

to the converter trim input.

14, 17

I

VMx

Voltage monitor input. Connect to the DC/DC converter positive sense line

or its +Vout pin.

9

I

VREF_CNTL

Voltage reference input used for DC output control and margining.

VREF_CNTL can be programmed to output the internal 1.25V reference

voltage. Pin should be left open if using VREF internal.

21

PWR

VDD

Power supply of the part.

7

GND

GND

Ground of the part. The SMM205 ground pin should be connected to the

ground of the device under control or to a star point ground. PCB layout

should take into consideration ground drops.

22

PWR

12VIN

12V power supply input internally regulated to either 3.6V or 5.5V. When

using the 3.6V internal regulator option the voltage input can be as low as

8V. It can be as high as 15V using the 5.5V internal regulator.

3

I

START

Programmable active high/low input. The START input is used solely for

enabling Active Control and/or margining.

5

I/O

READY

Programmable active high/low open drain output indicates that VM is at its

set point. When programmed as an active high output READY can also be

used as an input. When pulled low it will latch the state of the comparator

inputs.

23

CAP

VDD_CAP

External capacitor input used to filter the internal supply rail.

19

I

COMP1

12

I

COMP2

COMP1 and COMP2 are high impedance inputs, each connected internally

to a comparator and compared against the VREF_CNTL input. Each

comparator can be independently programmed to monitor for UV or OV.

The monitor level is set externally with a resistive voltage divider.

11

O

FAULT#

When either of the COMP1 or COMP2 inputs are in fault the open-drain

FAULT# output will be pulled low. A configuration option exists to disable

the FAULT# output while the device is margining.

13, 24-27

NC

NC

No Connect. Leave floating; do not connect anything to the NC pins.