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ACT8892 Datasheet(PDF) 23 Page - Active-Semi, Inc |
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ACT8892 Datasheet(HTML) 23 Page - Active-Semi, Inc |
23 / 32 page ACT8892 Rev 2, 01-Jul-15 Innovative PowerTM - 23 - www.active-semi.com Copyright © 2015-2017 Active-Semi, Inc. ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of NXP. Table 2: Control Pins PIN NAME OUTPUT nPBIN REG1, REG2, REG3 PWRHLD REG1, REG2, REG3 PWREN REG4, REG5, REG6, REG7 Control Sequences The ACT8892 features a variety of control sequences that are optimized for supporting system enable and disable, as well as Sleep mode and Hibernate mode of some application processors. Enabling/Disabling Sequence A typical enable sequence initiates as a result of asserting nPBIN, and begins by enabling REG3. When REG3 reaches its power-OK threshold, nRSTO is asserted low, resetting the microprocessor. REG1 is enabled after REG3 reaches its power-OK threshold for 2ms, REG2 is enabled after REG3 reaches its power-OK threshold for 4ms. If REG3 is above its power-OK threshold when the reset timer expires, nRSTO is de-asserted, allowing the microprocessor to begin its boot sequence. REG4, REG5, REG6 and REG7 can be enabled by asserting PWREN. During the boot sequence, the processor should read the HBRDY[ ] bit; if the value of HBRDY[ ] is 0 then the software should proceed with a typical enable sequence, whereas if the value of HBRDY[ ] is 1 then the software should proceed with a “wake from Hibernate Mode” routine. See the Hibernate Mode Sequence section for more information. During the boot sequence, the microprocessor must assert PWRHLD, holding REG1, REG2 and REG3 to ensure that the system remains powered after nPBIN is released. Once the power-up routine is completed, the system remains enabled after the push-button is released as long as either PWRHLD or PWREN are asserted high. If the processor does not assert PWRHLD before the user releases the push-button, the boot-up sequence is terminated and all regulators are disabled. This provides protection against "false-enable", when the push-button is accidentally depressed, and also ensures that the system remains enabled only if the processor successfully completes the boot-up sequence. As with the enable sequence, a typical disable sequence is initiated when the user presses the push-button, which interrupts the processor via the nPBSTAT output. The actual disable sequence is completely software-controlled, but typically involved initiating various “clean-up” processes before the processor finally de-asserts PWREN first, which disables REG4, REG5, REG6 and REG7, then de-asserts PWRHLD, which disables REG1, REG2 and REG3 after push-button is released, hence shuts the system down. Sleep Mode Sequence The ACT8892 supports some processors’ Sleep mode operation. Once a successful power-up routine has been completed, Sleep mode may be initiated through a variety of software-controlled mechanisms. Sleep mode is typically initiated when the user presses the push-button during normal operation. Pressing the push-button asserts the nPBIN input, which asserts the nPBSTAT output, which interrupts the processor. In response to this interrupt the processor should de-assert PWREN, disabling REG4, REG5, REG6 and REG7. PWRHLD should remain asserted during Sleep mode so that REG1, REG2 and REG3 remain enabled. When REG1, REG2 and REG3 standby voltage are preset to lower voltages for Sleep mode, the processor could assert VSEL pin when entering Sleep mode so that REG1, REG2 and REG3 outputs lower voltages to reduce power consumption in Sleep mode. Waking up from Sleep mode is typically initiated when the user presses the push-button again, which asserts nPBSTAT. Processors should respond by asserting PWREN, which turns on REG4, REG5, REG6 and REG7, and de-assert VSEL so that REG1, REG2 and REG3 go back to normal voltages, then normal operation may resume. Hibernate Mode Sequence The ACT8892 supports Hibernate mode of operation for some processors. Once a successful power-up routine is completed, Hibernate mode may be initiated through a variety of software- controlled mechanisms. Hibernate mode is typically initiated when the user presses the push-button during normal operation. Pressing the push-button asserts the nPBIN input, which asserts the nPBSTAT output to interrupt the processor. In : Typical value shown, actual delay time may vary from (T-1ms) x 88% to T x 112%, where T is the typical delay time setting. |
Número de pieza similar - ACT8892_17 |
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Descripción similar - ACT8892_17 |
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