S29GL01GP datasheet(76/82 Pages) CYPRESS

No. de pieza	S29GL01GP

Descripción Electrónicos	1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash with 90 nm MirrorBit Process Technology

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Fabricante Electrónico	CYPRESS [Cypress Semiconductor]

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76 / 82 page

Document Number: 002-00886 Rev. *B

Page 76 of 83

S29GL01GP

S29GL512P

S29GL256P

S29GL128P

13. Advance Information on S29GL-S Eclipse 65 nm MirrorBit

Power-On and Warm Reset Timing

At power on, the flash requires additional time in the reset state to self configure than it does during a warm reset. Table and

Figure 13.1 and Figure 13.2 detail the power on and warm reset timing requirements for the GL-P, and GL-S flash.

Notes:

1. N/A = Not Applicable.

2. For GL-S, tRP + tRH must not be less than tRPH.

Figure 13.1

Power-Up Reset Timing

Note:

The sum of tRP and tRH must be equal to or greater than tRPH.

Power On and Warm Reset Timing Requirements

Parameter

Description

Type

GL-P

GL-S

Power on Reset

tVCS

VCC Setup Time to first access

min

35 µs

300 µs

tVIOS

VIO Setup Time to first access

min

35 µs

300 µs

tRPH

RESET# Low to CE# Low

min

35 µs

tRP

RESET# Low to RESET# High

min

35 µs

200 ns (2)

tRH

RESET# High to CE# Low

min

200 ns

50 ns (2)

tCEH

CE# High to CE# Low

min

N/A

20 ns

Warm Reset

tRPH

RESET# Low to CE# Low

min

35 µs

tRP

RESET# Low to RESET# High

min

35 µs

200 ns (2)

tRH

RESET# High to CE# Low

min

200 ns

50 ns (2)

tCEH

CE# High to CE# Low

min

N/A

20 ns

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S29GL01GP Datasheet(PDF) 76 Page - Cypress Semiconductor

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