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AM49DL640BG85IS Datasheet(PDF) 11 Page - SPANSION

No. de pieza AM49DL640BG85IS
Descripción Electrónicos  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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Am49DL640BG
March 8, 2002
PR E L I M I N A R Y
MCP DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Tables 1-2 lists the device bus operations, the
inputs and control levels they require, and the result-
ing output. The following subsections describe each of
these operations in further detail.
Table 1.
Device Bus Operations—Flash Word Mode, CIOf = V
IH
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = pSRAM Address Input, Byte Mode,
SADD = Flash Sector Address, A
IN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1.
Other operations except for those indicated in this column are
inhibited.
2.
Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same
time.
3.
Don’t care or open LB#s or UB#s.
4.
If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC
= V
IH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by
40%.
5.
The sector protect and sector unprotect functions may also be
implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
6.
If WP#/ACC = V
IL, the two outermost boot sectors remain
protected. If WP#/ACC = VIH, the two outermost boot sector
protection depends on whether they were last protected or
unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If WP#/ACC = V
HH, all sectors will
be unprotected.
7.
Data will be retained in pSRAM.
8.
Data will be lost in pSRAM.
Operation
(Notes 1, 2)
CE#f
CE1#s
CE2s
OE#
WE#
Address
LB#s
UB#s RESET#
WP#/ACC
(Note 4)
DQ7–
DQ0
DQ15–
DQ8
Read from
Flash
(Note 7)
L
HH
LH
AIN
XX
H
L/H
DOUT
DOUT
(Note 8)
H
L
Write to Flash
(Note 7)
L
HH
HL
A
IN
XX
H
(Note 4)
D
IN
D
IN
(Note 8)
H
L
Standby
VCC ±
0.3 V
HH
X
X
X
X
X
VCC ±
0.3 V
H
High-Z
High-Z
Deep Power-down
Standby
VCC ±
0.3 V
HL
X
X
X
X
X
VCC ±
0.3 V
H
High-Z
High-Z
Output Disable
L
L
H
HH
X
X
X
H
L/H
High-Z
High-Z
HH
X
X
X
Flash Hardware
Reset
(Note 7)
X
HH
X
X
X
X
X
L
L/H
High-Z
High-Z
(Note 8)
H
L
Sector Protect
(Note 5)
(Note 7)
L
HH
HL
SADD, A6 = L,
A1 = H, A0 = L
XX
VID
L/H
DIN
X
(Note 8)
H
L
Sector
Unprotect
(Note 5)
(Note 7)
L
HH
HL
SADD, A6 = H,
A1 = H, A0 = L
XX
V
ID
(Note 6)
D
IN
X
(Note 8)
H
L
Temporary
Sector
Unprotect
(Note 7)
X
HH
XX
X
X
X
VID
(Note 6)
DIN
High-Z
(Note 8)
H
L
Read from pSRAM
H
L
H
L
H
AIN
LL
HX
D
OUT
D
OUT
H
L
High-Z
DOUT
LH
DOUT
High-Z
Write to pSRAM
H
L
H
X
L
AIN
LL
HX
D
IN
D
IN
H
L
High-Z
DIN
LH
D
IN
High-Z


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