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AK5522 Datasheet(PDF) 71 Page - Asahi Kasei Microsystems |
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AK5522 Datasheet(HTML) 71 Page - Asahi Kasei Microsystems |
71 / 84 page [AK5522] 017002311-E-00 2017/03 - 71 - PLL Slave Mode (Serial Control Mode) Figure 71. Power up Sequence (Serial Control mode, PLL Slave Mode) (1) Input LRCK and BICK after power on the power supplies. (2) Raise the PDN pin from “L” to “H”. The PDN pin should be held to “L” for more than 150 ns after power on the power supplies. (3) The Internal regulator for digital core powers up after 17.8ms (max.) from a rising edge of the PDN pin. This timing is counted by the internal oscillator. Register accesses will be valid after REGDO voltage is raised up. (4) Set “1” into PDPLLN bit after settling the REGDO pin and setting PLL slave mode. (5) The VREF pin outputs reference voltage after 17.9ms (max.@fs=48kHz) from PDPLLN bit = “1”. (6) The REGAO pin outputs 3.3V after 24.9ms (max.@fs=48kHz) from PDPLLN bit = “1”. (7) Set “1” into PDALN/PDARN bit after setting other registers. (8) The SDTO pin starts outputting A/D data after 64.6ms (max.@fs=48kHz) from PDADLN/PDADRN bit = “1”. (9) The MCLK pin starts outputting clock after 59.9ms (max.@fs=48kHz, Ref=LRCK) from PDPLLN bit = “1”. Wait time (5), (6), (8) and (9) depend on the sampling frequency as shown in the expressions below. (5): 10ms+378 n/fs (max.) (6): 5ms+953 n/fs (max.) (8): 3100 n/fs (max.) (9): 40ms+953 n/fs (max.) (Reference = LRCK) (9): 2ms+953 n/fs (max.) (Reference = BICK) Normal speed: n=1, Double speed: n=2, Quad speed: n=4 AVDD pin DVDD pin PDN pin (I) REGDO pin (O) (DVDD=3.3V) VREF pin (O) REGAO pin (O) (AVDD=5V) SDTO pin (O) REGDO pin (I) (DVDD=1.8V) REGAO pin (O) (AVDD=3.3V) PDADLN bit PDADRN bit LRCK pin (I) BICK pin (I) MCLK pin (O) PDPLLN bit (1) (2) Hi-Z (Pull-down) (9) (8) Output (3) Hi-Z Register access is valid Register access is valid (4) PLL Power down PLL Power up (7) (5) Hi-Z (Pull-down) Output (6) Output Hi-Z (Pull-down) |
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