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FAN3226 Datasheet(PDF) 19 Page - ON Semiconductor |
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FAN3226 Datasheet(HTML) 19 Page - ON Semiconductor |
19 / 26 page www.onsemi.com 19 VDD Bypass Capacitor Guidelines To enable this IC to turn a device on quickly, a local high- frequency bypass capacitor CBYP w ith low ESR and ESL should be connected betw een the VDD and GND pins w ith minimal trace length. This capacitor is in addition to bulk electrolytic capacitance of 10 µF to 47 µF commonly found on driver and controller bias circuits. A typical criterion for choosing the value of CBYP is to keep the r ipple voltage on the VDD supply to ≤5%. This is often achieved w ith a value ≥20 times the equivalent load capacitance CEQV, defined here as QGATE/VDD. Ceramic capacitors of 0.1 µF to 1 µF or larger are common choices, as are dielectrics, such as X5R and X7R w ith good temperature characteristics and high pulse current capability. If circuit noise affects normal operation, the value of CBYP may be increased to 50-100 times the CEQV, or CBYP may be split into tw o capacitors. One should be a larger value, based on equivalent load capacitance, and the other a s maller value, such as 1-10 nF mounted closest to the VDD and GND pins to carry the higher frequency components of the current pulses. The bypass capacitor must provide the pulsed current from both of the driver channels and, if the drivers are sw itching simultaneously, the combined peak current sourced from the CBYP w ould be tw ice as large as w hen a single channel is sw itching. Layout and Connection Guidelines The FA N3226-26 family of gate drivers incorporates fast-reacting input circuits, short propagation delays, and pow erful output stages capable of delivering current peaks over 2 A to facilitate voltage transition times from under 10 ns to over 150 ns. The follow ing layout and connection guidelines are strongly recommended: Keep high-current output and pow er ground paths separate logic and enable input signals and signal ground paths. This is espec ially critical w hen dealing w ith TTL-level logic thresholds at driver inputs and enable pins. Keep the driver as close to the load as possible to minimize the length of high-current traces. This reduces the ser ies inductance to improve high- speed sw itching, w hile reducing the loop area that can radiate EMI to the driver inputs and surrounding circuitry. If the inputs to a channel are not externally connected, the internal 100 k Ω resistors indicated on bloc k diagrams command a low output. In noisy environments, it may be necessary to tie inputs of an unused channel to V DD or GND using short traces to prevent noise from causing spur ious output sw itching. Many high-speed pow er circuits can be susceptible to noise injected from their ow n output or other external sources, possibly caus ing output re- triggering. These effects can be obvious if the circuit is tested in breadboard or non-optimal circuit layouts w ith long input, enable, or output leads. For best results, make connections to all pins as short and direct as possible. The FAN322x is compatible w ith many other industry-standard drivers. In single input parts w ith enable pins, there is an internal 100 k Ω res istor tied to VDD to enable the driver by default; this should be considered in the PCB layout. The turn-on and turn-off current paths should be minimized, as discussed in the follow ing section. Figure 49 show s the pulsed gate drive current path w hen the gate dr iver is supplying gate charge to turn the MOSFET on. The current is supplied from the local bypass capacitor, CBYP, and flow s through the driver to the MOSFET gate and to ground. To reach the high peak currents possible, the resistance and inductance in the path should be minimized. The localized CBYP acts to contain the high peak current pulses w ithin this driver- MOSFET circuit, preventing them from disturbing the sensitive analog circuitry in the PWM controller. PWM V DS V DD C BYP FAN322x Figure 49. Current Path for MOSFET Turn-on Figure 50 show s the current path w hen the gate dr iver turns the MOSFET off. Ideally, the driver shunts the current directly to the source of the MOSFET in a s mall circuit loop. For fast turn-off times, the resistance and inductance in this path should be minimized. PWM V DS V DD C BYP FAN322x Figure 50. Current Path for MOSFET Turn-off |
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