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NB6L239 Datasheet(PDF) 1 Page - ON Semiconductor |
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NB6L239 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 12 page © Semiconductor Components Industries, LLC, 2004 April, 2004 − Rev. 0 1 Publication Order Number: NB6L239/D NB6L239 2.5 V / 3.3 V Any Differential Clock IN to Differential LVPECL OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider Features The NB6L239 is a high−speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; B1/2/4/8 and B2/4/8/16. Both divider circuits drive a pair of differential LVPECL outputs. (More device information on page 7). • Maximum Clock Input Frequency, 3.0 GHz • Input Compatibility with LVDS/LVPECL/CML/HSTL • Rise/Fall Time 70 ps Typical • < 10 ps Typical Output−to−Output Skew • Ex. 622 MHz Input Generates 38.8 MHz to 622 MHz Outputs • Internal 50 W Termination Provided • Random Clock Jitter < 1 ps RMS • Divide−by−1 Edge of QA Aligned to QB Divided Output • Operating Range: V CC = 2.375 V to 3.465 V with VEE = 0 V • Master Reset for Synchronization of Multiple Chips • V BBAC Reference Output • Synchronous Output Enable/Disable CLK CLK EN Figure 1. Simplified Logic Diagram QB QB MR QA QA SELB1 SELB0 SELA1 SELA0 VT + MARKING DIAGRAM* http://onsemi.com QFN−16 MN SUFFIX CASE 485G XXXX XXXX ALYW XXXX = Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week Bottom View *For additional marking information, refer to Application Note AND8002/D. See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. ORDERING INFORMATION |
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