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ST62T62CM3 Datasheet(PDF) 48 Page - STMicroelectronics

No. de Pieza. ST62T62CM3
Descripción  8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, SAFE RESET, AUTO-RELOAD TIMER AND EEPROM
Descarga  78 Pages
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Fabricante  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST62T62CM3 Datasheet(HTML) 48 Page - STMicroelectronics

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ST62T52C ST62T62C/E62C
AUTO-RELOAD TIMER (Cont’d)
4.3.3 AR Timer Registers
AR Mode Control Register (ARMC)
Address: D5h
Read/Write
Reset status: 00h
The AR Mode Control Register ARMC is used to
program the different operating modes of the AR
Timer, to enable the clock and to initialize the
counter. It can be read and written to by the Core
and it is cleared on system reset (the AR Timer is
disabled).
Bit 7 = TLCD:
Timer Load Bit. This bit, when set,
will cause the contents of ARRC register to be
loaded into the counter and the contents of the
prescaler register, ARPSC, are cleared in order to
initialize the timer before starting to count. This bit
is write-only and any attempt to read it will yield a
logical zero.
Bit 6 = TEN
: Timer Clock Enable. This bit, when
set, allows the timer to count. When cleared, it will
stop the timer and freeze ARPSC and ARTSC.
Bit 5 = PWMOE:
PWM Output Enable. This bit,
when set, enables the PWM output on the ARTI-
Mout pin. When reset, the PWM output is disabled.
Bit 4 = EIE:
External Interrupt Enable. This bit,
when set, enables the external interrupt request.
When reset, the external interrupt request is
masked. If EIE is set and the related flag, EF, in
the ARSC0 register is also set, an interrupt re-
quest is generated.
Bit 3 = CPIE:
Compare Interrupt Enable. This bit,
when set, enables the compare interrupt request.
If CPIE is reset, the compare interrupt request is
masked. If CPIE is set and the related flag, CPF, in
the ARSC0 register is also set, an interrupt re-
quest is generated.
Bit 2 = OVIE:
Overflow Interrupt. This bit, when
set, enables the overflow interrupt request. If OVIE
is reset, the compare interrupt request is masked.
If OVIE is set and the related flag, OVF in the
ARSC0 register is also set, an interrupt request is
generated.
Bit 1-0 = ARMC1-ARMC0:
Mode Control Bits 1-0.
These are the operating mode control bits. The fol-
lowing bit combinations will select the various op-
erating modes:
AR Timer Status/Control Registers ARSC0 &
ARSC1. These registers contain the AR Timer sta-
tus information bits and also allow the program-
ming of clock sources, active edge and prescaler
multiplexer setting.
ARSC0 register bits 0,1 and 2 contain the interrupt
flags of the AR Timer. These bits are read normal-
ly. Each one may be reset by software. Writing a
one does not affect the bit value.
AR Status Control Register 0 (ARSC0)
Address: D6h
Read/Clear
Bits 7-3 = D7-D3:
Unused
Bit 2 = EF:
External Interrupt Flag. This bit is set by
any active edge on the external ARTIMin input pin.
The flag is cleared by writing a zero to the EF bit.
Bit 1 = CPF:
Compare Interrupt Flag. This bit is set
if the contents of the counter and the ARCP regis-
ter are equal. The flag is cleared by writing a zero
to the CPF bit.
Bit 0 = OVF:
Overflow Interrupt Flag. This bit is set
by a transition of the counter from FFh to 00h
(overflow). The flag is cleared by writing a zero to
the OVF bit.
70
TCLD
TEN
PWMOE
EIE
CPIE
OVIE ARMC1 ARMC0
ARMC1
ARMC0
Operating Mode
0
0
Auto-reload Mode
0
1
Capture Mode
10
Capture Mode with Reset
of ARTC and ARPSC
11
Load on External Edge
Mode
70
D7
D6
D5
D4
D3
EF
CPF
OVF


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