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ISL97650 Datasheet(PDF) 5 Page - Renesas Technology Corp |
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ISL97650 Datasheet(HTML) 5 Page - Renesas Technology Corp |
5 / 20 page ISL97650 FN9198 Rev.4.00 Page 5 of 20 April 17, 2009 Vth_VLOGIC(FBL) VLOGIC Buck Short Detection V(FBL) falling less than 0.9 V Vth_POUT(FBP) POUT Charge Pump Short Detection V(FBP) falling less than 0.9 V Vth_NOUT(FBN) NOUT Charge Pump Short Detection V(FBN) rising more than 0.4 V tFD Fault Delay Time to Chip Turns Off 52 ms START-UP SEQUENCING tSTART-UP Enable to AVDD Start Time CDEL = 220nF 80 ms IDELB_ON DELB Pull-Down Current or Resistance when Enabled by the Start-Up Sequence VDELB > 0.9V 36 50 70 µA VDELB < 0.9V 1.00 1.326 1.75 k IDELB_OFF DELB Pull-Down Current or Resistance when Disabled VDELB < 20V 500 nA CDEL Sequence Timing and Fault Time Out Capacitor 10 220 nF tVOFF AVDD to VOFF CDEL = 220nF 9 ms tVON VOFF to VON Delay CDEL = 220nF 20 ms tVON-SLICE VON to VON-SLICE Delay CDEL = 220nF 17 ms Electrical Specifications VIN = 12V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over-temperature from -40°C to +105°C, unless otherwise stated. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT Typical Performance Curves FIGURE 1. BOOST EFFICIENCY FIGURE 2. BOOST LOAD REGULATION 0 20 40 60 80 100 0 500 1000 1500 IO (mA) VIN = 12V VIN = 5V VIN = 12V VIN = 5V 0 0.02 0.04 0.06 0.08 0.10 0.12 0 500 1000 1500 2000 IO (mA) |
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