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ISL97650 Datasheet(PDF) 8 Page - Renesas Technology Corp |
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ISL97650 Datasheet(HTML) 8 Page - Renesas Technology Corp |
8 / 20 page ISL97650 FN9198 Rev.4.00 Page 8 of 20 April 17, 2009 Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION 1 LX1 Internal boost switch connection 2 LX2 Internal boost switch connection 3 CB Logic buck, boost strap pin 4 LXL Buck converter output 5, 18 NC No connect. Connect to die pad and GND for improved thermal efficiency. 6 VSUP Positive supply for charge pumps 7 FBL Logic buck feedback pin 8 CM2 Buck compensation network pin 9 CTL Input control for VON slice output 10 AGND2 Signal GND pin 11 DRN Lower reference voltage for VON slice output 12 COM VON slice output: when CTL = 1, COM is connected to SRC through a 5 resistor; when CTL = 0, COM is connected to DRN through a 30 resistor 13 POUT Positive charge pump out 14 C1- Charge pump capacitor 1, negative connection 15 C1+ Charge pump capacitor 1, positive connection 16 C2- Charge pump capacitor 2, negative connection 17 C2+ Charge pump capacitor 2, positive connection 19 FBP Positive charge pump feedback pin 20 VREF Reference voltage 21 FBN Negative charge pump feedback pin 22 PGND3 Power ground for VOFF, VON and VON slice 23 NOUT Negative charge pump output 24 VINL Logic buck supply voltage 25, 26 PGND2, 1 Boost power grounds 27 AGND1 Signal ground pin 28 VDC1 Internal supply decoupling capacitor 29 CDEL Delay capacitor for start up sequencing, soft-start and fault detection timers 30 ENL Buck enable for VLOGIC output 31 DELB Open drain NFET output to drive optional AVDD delay PFET 32 CM1 Boost compensation network pin 33 VIN Input voltage pin 34 FBB Boost feedback pin 35 EN Enable for boost, charge pumps and VON slice (independent of ENL) 36 VDC2 Internal supply decoupling capacitor Exposed Die Plate N/A Connect exposed die plate on rear of package to ACGND and the PGND1, 2 pins. See the section on "“Layout Recommendation” on page 19" for PCB layout thermal considerations. |
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