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ISL97650 Datasheet(PDF) 17 Page - Renesas Technology Corp

No. de pieza ISL97650
Descripción Electrónicos  4-Channel Integrated LCD Supply
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ISL97650 Datasheet(HTML) 17 Page - Renesas Technology Corp

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ISL97650
FN9198 Rev.4.00
Page 17 of 20
April 17, 2009
Start-Up Sequence
Figure 18 shows a detailed start-up sequence waveform. For a
successful power up, there should be 6 peaks at VCDLY. When
a fault is detected, the device will latch off until either EN is
toggled or the input supply is recycled.
When the input voltage is higher than 3.85V, VREF turns on, as
well as VLOGIC if the ENL is high. an internal current source
starts to charge CCDLY to an upper threshold using a fast ramp
followed by a slow ramp. During the initial slow ramp, the device
checks whether there is a fault condition. If no fault is found,
CCDLY is discharged after the first peak and VREF turns on.
Initially the boost is not enabled so AVDD rises to VIN-VDIODE
through the output diode. Hence, there is a step at AVDD
during this part of the start-up sequence. If this step is not
desirable, an external PMOS FET can be used to delay the
FIGURE 18. START-UP SEQUENCE
VCDLY
EN
VREF
VBOOST
VLOGIC
VOFF
DELAYED
VBOOST
VON
NORMAL
OPERATION
FAULT
PRESENT
START-UP SEQUENCE
TIMED BY CDLY
tSS
tSTART-UP
tVOFF
VIN
tVON
tVON-SLICE
VON SLICE
NOTE: Not to scale


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