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ISL97698 Datasheet(PDF) 11 Page - Renesas Technology Corp

No. de pieza ISL97698
Descripción Electrónicos  High Efficiency 2-Channel White LED Driver for Smartphone Backlighting
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ISL97698 Datasheet(HTML) 11 Page - Renesas Technology Corp

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ISL97698
FN8417 Rev.1.00
Page 11 of 21
Sep 7, 2017
Write Operation
A WRITE sequence requires an I2C START condition, followed by a valid Device Address Byte with the R/W bit set to ‘0’, a valid Register
Address Byte, a Data Byte, and a STOP condition. After each valid byte is sent, the ISL97698 (slave) responds with an ACK. When the
Write transaction is completed, the Master should generate a STOP condition. For sent data to be latched by the ISL97698, the STOP
condition should occur after a full byte (8-bits) is sent and ACK. If a STOP is generated in the middle of a byte transaction, the data will
be ignored. See Figure 20 for the ISL97698 I2C Write protocol.
Read Operation
A READ sequence requires the Master to first write to the ISL97698 to indicate the Register Address/pointer to read from. Send a
START condition, followed by a valid Device Address Byte with the R/W set to ‘0’, and then a valid Register Address Byte. Then the
Master generates either a Repeat START condition, or a STOP condition followed by a new START condition, and a valid Device Address
Byte with the R/W bit set to ‘1’. Then the ISL97698 is ready to send data to the Master from the requested Register Address.
The ISL97698 sends out the Data Byte by asserting control of the SDA pin while the Master generates clock pulses on the SCL pin.
When transmission of the desired data is complete, the Master generates a NACK condition followed by a STOP condition, and this
completes the I2C Read sequence. See Figure 21 for the ISL97698 I2C Read protocol.
FIGURE 20. I2C WRITE TIMING DIAGRAM
WRITE
DATA
SDA
(from Master)
SDA
(from Slave)
SCL
(from Master)
76 54 321 0
A
A 7 6 543 210
START
Device Address W
Register Pointer
7 6 543 210
A 765432 10 A
DATA
STOP
A
A
765432 10
76 54 321 0
Device Address = 27h
FIGURE 21. I2C READ TIMING DIAGRAM
WRITE
REGISTER
POINTER
SDA
(from Master)
SDA
(from Slave)
SCL
(from Master)
76543210
A
7 6543 210
A
A
7 6543 210 A
READ
DATA
SDA
(from Master)
SDA
(from Slave)
SCL
(from Master)
76543210 A
START
Device Address R
START
Device Address W
Register Pointer
STOP
NOTE: First send register pointer to
indicate the READ-back starting location
A
This STOP condition is optional (not
required) to do READ-back. The device
also supports repeated STARTs.
76543 21 0 A
(No ACK)
DATA
STOP
7654 32 10
A
76 5432 10
Device Address = 27h
A
76543210
Device Address = 27h


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