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MC100EP52DR2 Datasheet(PDF) 1 Page - ON Semiconductor |
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MC100EP52DR2 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 10 page © Semiconductor Components Industries, LLC, 2004 June, 2004 − Rev. 3 1 Publication Order Number: MC10EP52/D MC10EP52, MC100EP52 3.3V / 5VECL Differential Data and Clock D Flip−Flop The MC10EP/100EP52 is a differential data, differential clock D flip−flop. The device is pin and functionally equivalent to the EL52 device. Data enters the master portion of the flip−flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP52 allow the device to also be used as a negative edge triggered device. The EP52 employs input clamping circuitry so that under open input conditions (pulled down to VEE) the outputs of the device will remain stable. The 100 Series contains temperature compensation. • 330 ps Typical Propagation Delay • Maximum Frequency u 4 GHz Typical • PECL Mode: V CC = 3.0 V to 5.5 V with VEE = 0 V • NECL Mode: V CC = 0 V with VEE = −3.0 V to −5.5 V • Open Input Default State • Safety Clamp on Inputs • Q Output Will Default LOW with Inputs Open or at V EE ALYW SO−8 D SUFFIX CASE 751 MARKING DIAGRAMS* HEP52 L = Wafer Lot Y = Year W = Work Week H = MC10 K = MC100 A = Assembly Location ALYW KEP52 ALYW HP52 TSSOP−8 DT SUFFIX CASE 948R ALYW KP52 1 8 1 8 1 8 1 8 1 8 1 8 http://onsemi.com *For additional marking information, refer to Application Note AND8002/D. See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. ORDERING INFORMATION |
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