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CDCM7005RGZR Datasheet(PDF) 7 Page - Texas Instruments |
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CDCM7005RGZR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 40 page www.ti.com DEVICE CHARACTERISTICS CDCM7005 SCAS793A – JUNE 2005 – REVISED JUNE 2005 TIMING REQUIREMENTS (continued) over recommended ranges of supply voltage, load and operating free air temperature PARAMETER MIN TYP MAX UNIT tr/ tf Rise and fall time 20% to 80% of VINPP at 80 MHz to 800 MHz(4) 3 ns dutyVCXO Duty cycle of VCXO clock 40% 60% SPI/CONTROL REQUIREMENTS (see Figure 14) fCTRL_CLK CTRL_CLK frequency 20 MHz tsu1 CTRL_DATA to CTRL_CLK setup time 10 ns th2 CTRL_DATA to CTRL_CLK hold time 10 ns t3 CTRL_CLK high duration 25 ns t4 CTRL_CLK low duration 25 ns tsu5 CTRL_LE to CTRL_CLK setup time 10 ns tsu6 CTRL_CLK to CTRL_LE setup time 10 ns t7 CTRL_LE pulse width 20 ns tr/ tf Rise and fall time of CTRL_DATA CTRL_CLK, CTRL_LE from 20% to 80% of VCC 4 ns PD, RESET, HOLD, REF_SEL REQUIREMENTS tr / tf Rise and fall time of the PD, RESET, HOLD, REF_SEL signal from 20% to 80% of VCC 4 ns (4) Use a square wave for lower frequencies (< 80 MHz). over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT OVERALL fVCXO = 245.76 MHz, fREF_IN = 30.72 MHz, ICC_LVPECL PFD = 240 kHz, ICP = 2 mA, all outputs 210 260 mA are LVPECL and Div-by-8 (load, see Supply current (ICC over frequency see Figure 13) Figure 1 through Figure 4) fVCXO = 245.76 MHz, fREF_IN = 30.72 MHz, ICC_LVCMOS 120 150 mA PFD = 240 kHz, ICP = 2 mA, All outputs are LVCMOS and Div-by-8 (load, 10 pF) fIN = 0 MHz, VCC = 3.6 V, AVCC = 3.6 V, ICCPD Power-down current VCC_CP = 3.6 V, 100 300 µA VI = 0 V or VCC VO = 0 V or VCC– 0.8 V ±40 µA High-impedance state output current IOZ for Yx outputs VO = 0 V or VCC ±100 µA Voltage on I_REF_CP (external current 12 k Ω to GND at pin D8 (BGA), pin 22 VI_REF_CP 1.21 V path for accurate charge pump current) (QFN) VBB Output reference voltage VCC = 3 V – 3.6 V; IBB = –0.2 mA VCC–1.3 V CO Output capacitance for Yx VCC = 3.3 V, VO = 0 V or VCC 2 pF Input capacitance at PRI_REF and VI = 0 V or VCC, VI = 0 V or VCC 2.7 SEC_REF CI pF Input capacitance at CTRL_LE, VI = 0 V or VCC 2 CTRL_CLOCK, CTRL_DATA LVCMOS Output frequency, see (2), (3), Figure 6, Load = 5 pF to GND, 1 k Ω to V CC, 1 kΩ fclk 250 MHz and Figure 7 to GND VIK LVCMOS input clamp voltage VCC = 3 V, II = –18 mA –1.2 V LVCMOS input current for CTRL_LE, II VI = 0 V or VCC, VCC = 3.6 V ±5 µA CTRL_CLK, CTRL_DATA (1) All typical values are at VCC = 3.3 V, temperature = 25°C. (2) fclk can be up to 400 MHz in the typical operating mode (25°C / 3.3-V VCC). The total power consumption limit of 700 mW for the BGA package can be violated if several LVCMOS outputs switch at high frequency (see Figure 3 and Figure 4). (3) Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output signal swing may no longer meet the output specification. 7 |
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