Motor de Búsqueda de Datasheet de Componentes Electrónicos
Selected language     Spanish  ▼

Delete All
ON OFF
ALLDATASHEET.ES

X  

Preview PDF Download HTML

VSC8114 Datasheet(PDF) 5 Page - Vitesse Semiconductor Corporation

No. de Pieza. VSC8114
Descripción  ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
Descarga  24 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricante  VITESSE [Vitesse Semiconductor Corporation]
Página de inicio  http://www.vitesse.com
Logo 

VSC8114 Datasheet(HTML) 5 Page - Vitesse Semiconductor Corporation

 
Zoom Inzoom in Zoom Outzoom out
 5 / 24 page
background image
G52185-0, Rev 4.0
© VITESSE SEMICONDUCTOR CORPORATION
Page 5
11/1/99
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8114
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Equipment Loopback
The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is
set high, the Equipment Loopback mode is activated and the high speed transmit data generated from the paral-
lel to serial conversion of the low speed data (TXIN[7:0]) is selected and converted back to parallel data in the
receiver section and presented to the low speed parallel outputs (RXOUT[7:0]). See Figure 4. The internally
generated 622MHz clock is used to generate the low speed receive clock output (RXLSCKOUT). In Equipment
Loopback mode the transmit data (TXIN[7:0]) is serialized and presented to the high speed output
(TXDATAOUT) using the clock generated by the on-chip clock multiplier unit.
CRU Equipment Loopback
Exactly the same as equipment loopback, the point where the transmit data is looped back is moved all the
way back to the high speed I/O. When the CRUEQLP signal is set high, transmit data is looped back to the
CRU, replacing RXDATAIN±
Figure 4: Equipment Loopback Data Path
Split Loopback
Equipment and facility loopback modes can be enabled simultaneously. In this case, high-speed serial data
received (RXDATAIN) is mux’d through to the high-speed serial outputs (TXDATAOUT). The low-speed trans-
mit byte-wide bus (TXIN[7:0]) and (TXLSCKIN) is mux’d into the low-speed byte-wide receive output bus
(RXOUT[7:0]) and (RXLSCKOUT). See Figure 5.
Figure 5: Split Loopback Datapath
D Q
D
Q
1:8
Serial to
Parallel
Q
D
RXDATAIN
TXDATAOUT
RXOUT[7:0]
Q
D
8:1
Parallel to
Serial
TXIN[7:0]
÷ 8
PLL
÷ 8
RXLSCKOUT
TXLSCKIN
TXLSCKOUT
0
1
EQULOOP
D
Q
D
Q
1:8
Serial to
Parallel
Q
D
RXDATAIN
TXDATAOUT
RXOUT[7:0]
Q
D
8:1
Parallel to
Serial
TXIN[[7:0]
0
1
CRU
RXCLKIN
TXLSCKIN
RXLSCKOUT
DSBLCRU
Recovered
Clock


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24 


Datasheet Download




Enlace URL




Privacy Policy
ALLDATASHEET.ES
Does ALLDATASHEET help your business so far?  [ DONATE ]  

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Favorito   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn