Motor de Búsqueda de Datasheet de Componentes Electrónicos
Selected language     Spanish  ▼

Delete All
ON OFF
ALLDATASHEET.ES

X  

Preview PDF Download HTML

VSC8114 Datasheet(PDF) 2 Page - Vitesse Semiconductor Corporation

No. de Pieza. VSC8114
Descripción  ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
Descarga  24 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricante  VITESSE [Vitesse Semiconductor Corporation]
Página de inicio  http://www.vitesse.com
Logo 

VSC8114 Datasheet(HTML) 2 Page - Vitesse Semiconductor Corporation

 
Zoom Inzoom in Zoom Outzoom out
 2 / 24 page
background image
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8114
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Page 2
© VITESSE SEMICONDUCTOR CORPORATION
G52185-0, Rev 4.0
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
11/1/99
detector circuit which is used to provide frame pluses during the A1, A2 boundary in the serial to parallel con-
verter. This only occurs when OOF is high. Both internal and external LOS functions are supported.
The VSC8114 provides the parity error detection and generation for the 8 bit data bus. On the receive side,
the parity of the 8 bit data outputs is generated. On the transmit side, the parity of the 8 bit data input is calcu-
lated and compared with the received parity input.
VSC8114 Block Diagram
Transmit Section
Byte-wide data is presented to TXIN[7:0] and is clocked into the part on the rising edge of TXLSCKIN.
See Figure 1. The data is then serialized (MSB leading) and presented to the TXDATAOUT+/- pins. The serial
output stream is synchronized to the CMU generated clock which is a phase locked and frequency scaled ver-
DQ
0
1
0
1
D
Q
0
1
0
1
8
RXOUT[7:0]
RXLSCKOUT
FP
OOF
EQULOOP
TXDATAOUT+/-
8
TXIN[7:0]
TXLSCKOUT
TXLSCKIN
FACLOOP
CMU
Divide-by-8
1:8
DEMUX
FRAMER
Divide-by-8
8:1
MUX
Parity/
CRU
RXDATAIN+/-
RXCLKIN+/-
DSBLCRU
0
1
0
1
1
0
losdet
REFCLKP+/-
LOSDETEN_
REC-DATA
REC-CLK
REFSEL
Parity Chk
REG
TXINP
TXPERR
RXOUTP
REG
LOSTTL
LOSPECL
0
1
LOOPTIM0
1
0
CRUREFSEL
CRUREFCLK
0
1
CRUEQLP
RESET


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24 


Datasheet Download




Enlace URL




Privacy Policy
ALLDATASHEET.ES
Does ALLDATASHEET help your business so far?  [ DONATE ]  

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Favorito   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn