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SM5024AL1H Datasheet(PDF) 2 Page - Nippon Precision Circuits Inc |
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SM5024AL1H Datasheet(HTML) 2 Page - Nippon Precision Circuits Inc |
2 / 9 page SM5024 series NIPPON PRECISION CIRCUITS INC.—2 PINOUT (Top view) PIN DESCRIPTION BLOCK DIAGRAM Notes. The SM5024 series reduce crystal current by limiting driving current of oscillating-stage inverter and inhibiting oscillating amplitude. Depending on the characteristics of using crystal or the mounting condition, they may not oscillate normally. Please evaluate the oscillation start-up characteris- tics adequately with your actual device. When this device is used for buffer application, please pay attention to input amplitude to the XT pin. If it’s low input amplitude, the SM5024 series may not operate normally. Name I/O Description INHN I Output state control input. High impedance when LOW. Pull-up resistor built-in. XT I Amplifier input Crystal connection pins. Crystal is connected between XT and XTN. XTN O Amplifier output VSS – Ground Q O Output. Output frequency (fO, fO/2, fO/4, fO/8) determined by internal connection VDD – Supply voltage INHN = LOW active 1 XT VSS Q VDD 2 3 6 5 4 XTN INHN CGp CDp Rf CGn CDn XT VSS VDD Q XTN INHN 1/2 1/2 1/2 |
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