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DS90UB962-Q1 Datasheet(PDF) 69 Page - Texas Instruments |
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DS90UB962-Q1 Datasheet(HTML) 69 Page - Texas Instruments |
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69 / 169 page  69 DS90UB962-Q1 www.ti.com SNLS573 – AUGUST 2018 Product Folder Links: DS90UB962-Q1 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated 7.6.1.8 BCC_WATCHDOG_CONTROL Register The BCC watchdog timer allows termination of a control channel transaction if it fails to complete within a programmed amount of time. Table 26. BCC_WATCHDOG_CONTROL Register (Address 0x07) BIT FIELD TYPE DEFAULT DESCRIPTION 7:1 BCC_WATCHDOG _TIMER R/W 0x7F The watchdog timer allows termination of a control channel transaction if it fails to complete within a programmed amount of time. This field sets the Bi-directional Control Channel Watchdog Timeout value in units of 2 milliseconds. This field should not be set to 0. 0 BCC_WATCHDOG _TIMER_DISABLE R/W 0 Disable Bi-directional Control Channel Watchdog Timer 1: Disables BCC Watchdog Timer operation 0: Enables BCC Watchdog Timer operation 7.6.1.9 I2C_CONTROL_1 Register Table 27. I2C_CONTROL_1 Register (Address 0x08) BIT FIELD TYPE DEFAULT DESCRIPTION 7 LOCAL_WRITE _DISABLE R/W 0 Disable Remote Writes to Local Registers Setting this bit to a 1 will prevent remote writes to local device registers from across the control channel. This prevents writes to the Deserializer registers from an I2C master attached to the Serializer. Setting this bit does not affect remote access to I2C slaves at the Deserializer. 6:4 I2C_SDA_HOLD R/W 0x1 Internal SDA Hold Time This field configures the amount of internal hold time provided for the SDA input relative to the SCL input. Units are 50 nanoseconds. 3:0 I2C_FILTER_DEPTH R/W 0xC I2C Glitch Filter Depth This field configures the maximum width of glitch pulses on the SCL and SDA inputs that is rejected. Units are 5 nanoseconds. 7.6.1.10 I2C_CONTROL_2 Register Table 28. I2C_CONTROL_2 Register (Address 0x09) BIT FIELD TYPE DEFAULT DESCRIPTION 7:4 SDA_OUTPUT_SETUP R/W 0x1 Remote Ack SDA Output Setup When a Control Channel (remote) access is active, this field configures setup time from the SDA output relative to the rising edge of SCL during ACK cycles. Setting this value will increase setup time in units of 640ns. The nominal output setup time value for SDA to SCL when this field is 0 is 80ns. 3:2 SDA_OUTPUT_DELAY R/W 0x0 SDA Output Delay This field configures additional delay on the SDA output relative to the falling edge of SCL. Setting this value will increase output delay in units of 40ns. Nominal output delay values for SCL to SDA are: 00: 240ns 01: 280ns 10: 320ns 11: 360ns 1 I2C_BUS_TIMER _SPEEDUP R/W 0 Speed up I2C Bus Watchdog Timer 1: Watchdog Timer expires after approximately 50 microseconds 0: Watchdog Timer expires after approximately 1 second. 0 I2C_BUS_TIMER _DISABLE R/W 0 Disable I2C Bus Watchdog Timer When the I2C Watchdog Timer may be used to detect when the I2C bus is free or hung up following an invalid termination of a transaction. If SDA is high and no signalling occurs for approximately 1 second, the I2C bus will assumed to be free. If SDA is low and no signaling occurs, the device will attempt to clear the bus by driving 9 clocks on SCL |
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