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DSLVDS1047 Datasheet(PDF) 19 Page - Texas Instruments |
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DSLVDS1047 Datasheet(HTML) 19 Page - Texas Instruments |
19 / 26 page 8 7 Decoupling Cap 6 5 4 3 2 1 9 10 11 12 13 14 15 16 VCC DIN2 DIN1 EN DIN3 DIN4 EN* GND DOUT4- DOUT4+ DOUT3+ DOUT3- DOUT2- DOUT2+ DOUT1+ DOUT1- DS90LV047A 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 ROUT2 ROUT1 EN ROUT3 ROUT4 EN* GND DS90LV048A RIN4- RIN4+ RIN3+ RIN3- RIN2- RIN2+ RIN1+ RIN1- LVCMOS Inputs VCC Decoupling Cap Series Termination (optional) Series Termination (optional) LVCMOS Outputs Input Termination (Required) 19 DSLVDS1047 www.ti.com SNLS623 – SEPTEMBER 2018 Product Folder Links: DSLVDS1047 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Layout Guidelines (continued) Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination to the receiver inputs must be minimized. The distance between the termination resistor and the receiver should be < 10 mm (12 mm maximum). 11.2 Layout Example Figure 26. Layout Recommendation |
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