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NV25128WF Datasheet(PDF) 3 Page - ON Semiconductor |
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NV25128WF Datasheet(HTML) 3 Page - ON Semiconductor |
3 / 13 page NV25128WF www.onsemi.com 3 Table 4. PIN CAPACITANCE (Note 5) (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V) Symbol Test Conditions Min Typ Max Units COUT Output Capacitance (SO) VOUT = 0 V 8 pF CIN Input Capacitance (CS, SCK, SI, WP, HOLD) VIN = 0 V 8 pF 5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. Table 5. A.C. CHARACTERISTICS (VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) (Note 6) Symbol Parameter Min Max Units fSCK Clock Frequency DC 10 MHz tSU Data Setup Time 10 ns tH Data Hold Time 10 ns tWH SCK High Time 40 ns tWL SCK Low Time 40 ns tLZ HOLD to Output Low Z 25 ns tRI (Note 7) Input Rise Time 2 ms tFI (Note 7) Input Fall Time 2 ms tHD HOLD Setup Time 0 ns tCD HOLD Hold Time 10 ns tV Output Valid from Clock Low 40 ns tHO Output Hold Time 0 ns tDIS Output Disable Time 20 ns tHZ HOLD to Output High Z 25 ns tCS CS High Time 40 ns tCSS CS Setup Time 30 ns tCSH CS Hold Time 30 ns tCNS CS Inactive Setup Time 20 ns tCNH CS Inactive Hold Time 20 ns tWPS WP Setup Time 10 ns tWPH WP Hold Time 10 ns tWC (Note 8) Write Cycle Time 5 ms 6. AC Test Conditions: Input Pulse Voltages: 0.3 VCC to 0.7 VCC Input rise and fall times: ≤ 10 ns Input and output reference voltages: 0.5 VCC Output load: current source IOL max/IOH max; CL = 30 pF 7. This parameter is tested initially and after a design or process change that affects the parameter. 8. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle. Table 6. POWER−UP TIMING (Notes 7, 9) Symbol Parameter Min Max Units tPUR Power−up to Read Operation 0.1 1 ms tPUW Power−up to Write Operation 0.1 1 ms 9. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. |
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