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S71PL129JB0BAW9P0 Datasheet(PDF) 82 Page - SPANSION |
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S71PL129JB0BAW9P0 Datasheet(HTML) 82 Page - SPANSION |
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82 / 149 page  82 pSRAM Type 6 pSRAM_Type06_14_A1 Ocotober 16, 2004 Advance Info rmation AC Test Conditions tOH Output Data Hold Time 10 — ns tPM Page Mode Time 70 10000 ns tPC Page Mode Cycle Time 30 — ns tAA Page Mode Address Access Time — 30 ns tAOH Page Mode Output Data Hold Time 10 — ns tWC Write Cycle Time 70 10000 ns tWP Write Pulse Width 50 — ns tCW Chip Enable to End of Write 70 — ns tBW Data Byte Control to End of Write 60 — ns tAW Address Valid to End of Write 60 — ns tAS Address Set-up Time 0 — ns tWR Write Recovery Time 0 — ns tCEH Chip Enable High Pulse Width 10 — ns tWEH Write Enable High Pulse Width 6 — ns tODW WE# Low to Output High-Z — 20 ns tOEW WE# High to Output Active 0 ns tDS Data Set-up Time 30 — ns tDH Data Hold Time 0 — ns tCS CE2 Set-up Time 0 — ns tCH CE2 Hold Time 300 — µs tDPD CE2 Pulse Width 10 — ms tCHC CE2 Hold from CE1# 0 — ns tCHP CE2 Hold from Power On 30 — µs Parameter Condition Output load 30 pF + 1 TTL Gate Input pulse level VDD - 0.2 V, 0.2 V Timing measurements VDD x 0.5 Reference level VDD x 0.5 tR, tF 5 ns Symbol Parameter Min Max Unit |
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