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S71PL129JB0BAW9B2 Datasheet(PDF) 18 Page - SPANSION |
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S71PL129JB0BAW9B2 Datasheet(HTML) 18 Page - SPANSION |
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18 / 149 page  18 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Info rmation Pin Description Amax–A0 = Address bus DQ15–DQ0 = 16-bit data inputs/outputs/float CE# = Chip Enable Inputs OE# = Output Enable Input WE# = Write Enable VSS = Device Ground NC = Pin Not Connected Internally RY/BY# = Ready/Busy output and open drain. When RY/BY#= VIH, the device is ready to accept read operations and commands. When RY/BY#= VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset operation. WP#/ACC = Write Protect/Acceleration Input. When WP#/ACC= VIL, the highest and lowest two 4K-word sectors are write protected regardless of other sector protection configurations. When WP#/ ACC= VIH, these sector are unprotected unless the DYB or PPB is programmed. When WP#/ACC= 12V, program and erase operations are accelerated. VIO = Input/Output Buffer Power Supply 2.7 V to 3.6 V VCC =Chip Power Supply (2.7 V to 3.6 V or 2.7 to 3.3 V) RESET# = Hardware Reset Pin CE1#, CE2# = Chip Enable Inputs. CE1# controls the 64Mb in Banks 1A and 1B. CE2# controls the 64 Mb in Banks 2A and 2B. Notes: 1. Amax = A21 Logic Symbol max+1 16 DQ15–DQ0 Amax–A0 CE# OE# WE# RESET# RY/BY# WP#/ACC VIO (VCCQ) |
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