Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
S71PL129JB0BAW9U2 Datasheet(PDF) 20 Page - SPANSION |
|
S71PL129JB0BAW9U2 Datasheet(HTML) 20 Page - SPANSION |
20 / 149 page 20 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Info rmation Random Read (Non-Page Read) Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable ad- dresses and stable CE# to valid data at the output inputs. The output enable access time is the delay from the falling edge of the OE# to valid data at the out- put inputs (assuming the addresses have been stable for at least tACC–tOE time). Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. Address bits Amax–A3 select an 8 word page, and address bits A2–A0 select a specific word within that page. This is an asyn- chronous operation with the microprocessor supplying the specific word location. The random or initial page access is tACC or tCE and subsequent page read ac- cesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE1# and CE#2 are deasserted (=VIH), the reassertion of CE1# or CE#2 for subsequent access has access time of tACC or tCE. Here again, CE1#/CE#2 selects the device and OE# is the output control and should be used to gate data to the output inputs if the device is selected. Fast page mode accesses are obtained by keeping Amax–A3 constant and changing A2–A0 to select the specific word within that page. Simultaneous Read/Write Operation In addition to the conventional features (read, program, erase-suspend read, and erase-suspend program), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation). The bank can be selected by bank addresses (A21–A19) with zero latency. The simultaneous operation can execute multi-function mode in the same bank. Table 2. Page Select Word A2 A1 A0 Word 0 0 0 0 Word 1 0 0 1 Word 2 0 1 0 Word 3 0 1 1 Word 4 1 0 0 Word 5 1 0 1 Word 6 1 1 0 Word 7 1 1 1 Bank CE1# CE2# PL129J: A21–A20 Bank 1A 0 1 00 Bank 1B 0 1 01, 10, 11 |
Número de pieza similar - S71PL129JB0BAW9U2 |
|
Descripción similar - S71PL129JB0BAW9U2 |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |