SMH4042ASBHM datasheet(11/28 Pages) SUMMIT

No. de pieza	SMH4042ASBHM

Descripción Electrónicos	Distributed Power Hot-Swap Controller for CompactPCI

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Fabricante Electrónico	SUMMIT [Summit Microelectronics, Inc.]

Página de inicio	http://www.summitmicro.com

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11 / 28 page

2070

9.1 5/27/03

SMH4042A

SUMMIT MICROELECTRONICS, Inc.

11

BUS INTERFACE

GENERAL DESCRIPTION

The I2C bus is a two-way, two-line serial communication

between different integrated circuits. The two lines are:

a serial Data line (SDA) and a serial Clock line (SCL). All

Summit Microelectronics parts support a 100kHz clock

rate, and some support the alternative 400kHz clock.

Check Table 2 for the value of fSCL. The SDA line must

be connected to a positive supply by a pull-up resistor

located on the bus. Summit parts have a Schmitt input on

both lines. See Figure 5 and Table 2 for waveforms and

timing on the bus. One bit of Data is transferred during

each Clock pulse. The Data must remain stable when the

Clock is high.

Figure 5. I2C Timing Diagram

Table 2. I2C AC Operating Characteristics

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Note 1 - Guaranteed by Design

tF

tR

tLOW

tHIGH

tHD:SDA

tSU:SDA

tBUF

tDH

tHD:DAT

tSU:DAT

tSU:STO

SCL

SDA In

SDA Out

tAA

2070 Fig05

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