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SMH4042AGBLM Datasheet(PDF) 11 Page - Summit Microelectronics, Inc. |
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SMH4042AGBLM Datasheet(HTML) 11 Page - Summit Microelectronics, Inc. |
11 / 28 page 2070 9.1 5/27/03 SMH4042A SUMMIT MICROELECTRONICS, Inc. 11 BUS INTERFACE GENERAL DESCRIPTION The I2C bus is a two-way, two-line serial communication between different integrated circuits. The two lines are: a serial Data line (SDA) and a serial Clock line (SCL). All Summit Microelectronics parts support a 100kHz clock rate, and some support the alternative 400kHz clock. Check Table 2 for the value of fSCL. The SDA line must be connected to a positive supply by a pull-up resistor located on the bus. Summit parts have a Schmitt input on both lines. See Figure 5 and Table 2 for waveforms and timing on the bus. One bit of Data is transferred during each Clock pulse. The Data must remain stable when the Clock is high. Figure 5. I2C Timing Diagram Table 2. I2C AC Operating Characteristics 2037 Table02 2.0 l o b m y Sr e t e m a r a Ps n o i t i d n o C. n i M. p y T. x a Ms t i n U f L C S y c n e u q e r f k c o l c L C S0 0 0 1z H k t W O L d o i r e p w o l k c o l C7 . 4s µ t H G I H d o i r e p h g i h k c o l C0 . 4s µ t F U B ) 1 ( e m i t e e r f s u Bn o i s s i m s n a r t w e n e r o f e B7 . 4s µ t A T S : U S e m i t p u t e s n o i t i d n o c t r a t S7 . 4s µ t A T S : D H e m i t d l o h n o i t i d n o c t r a t S0 . 4s µ t O T S : U S e m i t p u t e s n o i t i d n o c p o t S7 . 4s µ t A A t u p t u o d i l a v o t e g d e k c o l C) n e l c y c ( A D S d i l a v o t w o l L C S2 . 05 . 3s µ t H D e m i t d l o h t u O a t a De g n a h c A D S o t ) 1 + n e l c y c ( w o l L C S2 . 0s µ t R ) 1 ( e m i t e s i r A D S d n a L C S 0 0 0 1s n t F ) 1 ( e m i t l l a f A D S d n a L C S 0 0 3s n t T A D : U S e m i t p u t e s n I a t a D0 5 2s n t T A D : D H e m i t d l o h n I a t a D0 s n I TA D S d n a L C S r e t l i f e s i o Nn o i s s e r p p u s e s i o N0 0 1s n t R W e m i t e l c y c e t i r W 5s m Note 1 - Guaranteed by Design tF tR tLOW tHIGH tHD:SDA tSU:SDA tBUF tDH tHD:DAT tSU:DAT tSU:STO SCL SDA In SDA Out tAA 2070 Fig05 |
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