Si5320
10
Rev. 2.3
Wander/Jitter at 1600 Hz Bandwidth
(BWSEL[1:0] = 01 and DBLBW = 0)
Jitter Tolerance (see Figure 7)
JTOL(PP)
f = 16 Hz
1000
—
—
ns
f = 160 Hz
100
—
—
ns
f = 1600 Hz
10
—
—
ns
CLKOUT RMS Jitter Generation
FEC[1:0] = 00
JGEN(RMS)
12 kHz to 20 MHz
—
0.82
1.0
ps
50 kHz to 80 MHz
—
0.26
0.35
ps
CLKOUT RMS Jitter Generation
FEC[1:0] = 01, 10
JGEN(RMS)
12 kHz to 20 MHz
—
0.79
1.0
ps
50 kHz to 80 MHz
—
0.26
0.35
ps
CLKOUT Peak-Peak Jitter Generation
FEC[1:0] = 00
JGEN(PP)
12 kHz to 20 MHz
—
7.3
10.0
ps
50 kHz to 80 MHz
—
3.8
5.0
ps
CLKOUT Peak-Peak Jitter Generation
FEC[1:0] = 01, 10
JGEN(PP)
12 kHz to 20 MHz
—
7.1
10.0
ps
50 kHz to 80 MHz
—
4.3
5.0
ps
Jitter Transfer Bandwidth (see Figure 10)
FBW
BW = 1600 Hz
—
1600
—
Hz
Wander/Jitter Transfer Peaking
JP
< 1600 Hz
—
0.0
0.1
dB
Wander/Jitter at 3200 Hz Bandwidth
(BWSEL[1:0] = 01 and DBLBW = 1)
Jitter Tolerance (see Figure 7)
f = 32 Hz
500
—
—
ns
f = 320 Hz
50
—
—
ns
f= 3200 Hz
5
—
—
ns
CLKOUT RMS Jitter Generation
FEC[1:0] = 00
JGEN(RMS)
12 kHz to 20 MHz
—
0.72
0.9
ps
50 kHz to 80 MHz
—
0.24
0.3
ps
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Notes:
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of
nanoseconds per millisecond. The equivalent ps/
µs unit is used here since the maximum phase transient magnitude for the
Si5320 (tPT_MTIE) never reaches one nanosecond.