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CAT5111UI-01SOIC Datasheet(PDF) 2 Page - Catalyst Semiconductor

No. de pieza CAT5111UI-01SOIC
Descripción Electrónicos  100-Tap Digitally Programmable Potentiometer
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Fabricante Electrónico  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT5111UI-01SOIC Datasheet(HTML) 2 Page - Catalyst Semiconductor

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Doc. No. 2009, Rev. R
CAT5113
of the CAT5113 and is active low. When in a high
state, activity on the
INC and U/D inputs will not
affect or change the position of the wiper.
DEVICE OPERATION
The CAT5113 operates like a digitally controlled
potentiometer with RH and RL equivalent to the high
and low terminals and RW equivalent to the mechanical
potentiometer's wiper. There are 100 available tap
positions including the resistor end points, RH and RL.
There are 99 resistor elements connected in series
between the RH and RL terminals. The wiper terminal is
connected to one of the 100 taps and controlled by three
inputs,
INC, U/D and CS. These inputs control a seven-
bit up/down counter whose output is decoded to select
the wiper position. The selected wiper position can be
stored in nonvolatile memory using the
INC and
CS inputs.
With
CS set LOW the CAT5113 is selected and will
respond to the U/
D and INC inputs. HIGH to LOW
transitions on
INC wil increment or decrement the
wiper (depending on the state of the U/
D input and
seven-bit counter). The wiper, when at either fixed
terminal, acts like its mechanical equivalent and does
not move beyond the last position. The value of the
counter is stored in nonvolatile memory whenever
CS
transitions HIGH while the
INC input is also HIGH. When
the CAT5113 is powered-down, the last stored wiper
counter position is maintained in the nonvolatile memory.
When power is restored, the contents of the memory are
recalled and the counter is set to the value stored.
With
INC set low, the CAT5113 may be de-selected
and powered down without storing the current wiper
position in nonvolatile memory. This allows the
system to always power up to a preset value stored
in nonvolatile memory.
PIN DESCRIPTIONS
INC
INC
INC
INC
INC: Increment Control Input
The
INC input moves the wiper in the up or down direction
determined by the condition of the U/
D input.
U/
D
D
D
D
D: Up/Down Control Input
The U/
D input controls the direction of the wiper
movement. When in a high state and
CS is low, any high-
to-low transition on
INC will cause the wiper to move one
increment toward the RH terminal. When in a low state
and
CS is low, any high-to-low transition on INC will
cause the wiper to move one increment towards the
RL terminal.
RH: High End Potentiometer Terminal
RH is the high end terminal of the potentiometer. It is not
required that this terminal be connected to a potential
greater than the RL terminal. Voltage applied to the RH
terminal cannot exceed the supply voltage, VCC or go
below ground, GND.
RW: Wiper Potentiometer Terminal
RW is the wiper terminal of the potentiometer. Its position
on the resistor array is controlled by the control inputs,
INC,
U/
D and CS. Voltage applied to the RW terminal cannot
exceed the supply voltage, VCC or go below ground, GND.
RL: Low End Potentiometer Terminal
RL is the low end terminal of the potentiometer. It is not
required that this terminal be connected to a potential
less than the RH terminal. Voltage applied to the RL
terminal cannot exceed the supply voltage, VCC or go
below ground, GND. RL and RH are electrically
interchangeable.
CS
CS
CS
CS
CS: Chip Select
The chip select input is used to activate the control input
PIN FUNCTIONS
Pin Name
Function
INC
Increment Control
U/
D
Up/Down Control
RH
Potentiometer High Terminal
GND
Ground
RW
Potentiometer Wiper Terminal
RL
Potentiometer Low Terminal
CS
Chip Select
VCC
Supply Voltage
PIN CONFIGURATION
DIP Package (P, L)
TSSOP Package (U, Y)
MSOP Package (R, Z)
CS
INC
VCC
U
/D
GND
RH
RL
RW
1
2
3
4
8
7
6
5
INC
VCC
CS
U
/D
GND
RW
RH
RL
1
2
3
4
8
7
6
5
VCC
R
R
GND
R
INC
U/
D
CS
W
L
H
1
2
3
4
8
7
6
5
CS
INC
VCC
U
/D
GND
RH
RL
RW
1
2
3
4
8
7
6
5
SOIC Package (S, V)


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