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CAT25C09VE-TE13 Datasheet(Hoja de datos) 8 Page - Catalyst Semiconductor

No. de Pieza. CAT25C09VE-TE13
Descripción  1K/2K/4K/8K/16K SPI Serial CMOS EEPROM
Descarga  12 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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8
CAT25C11/03/05/09/17
Doc. No. 1017, Rev. J
Figure 6. Write Instruction Timing
SK
SI
SO
00
00
X*
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
012345678
21
22
23
24
25
26
27
28
29
30
31
CS
OPCODE
DATA IN
HIGH IMPEDANCE
BYTE ADDRESS*
**
AN
A0
*Please check the Byte Address Table
X = 0 for CAT25C11, CAT25C03, CAT25C09 and CAT25C17; X = A8 for CAT25C05
Note: Dashed Line= mode (1, 1) – –––
device. If the write operation is initiated immediately after
the WREN instruction without
CS being brought high,
the data will not be written to the array because the write
up to 16 bytes of data to the CAT25C11/03/05 and 32
bytes of data for 25C09/17. After each byte of data
received, lower order address bits are internally
incremented by one; the high order bits of address
willremain constant.The only restriction is that the X
(X=16 for 25C11/03/05 and X=32 for 25C09/17) bytes
must reside on the same page. If the address counter
reaches the end of the page and clock continues, the
counter will “roll over” to the first address of the page and
overwrite any data that may have been written. The
CAT25C11/03/05/09/17 is automatically returned to the
write disable state at the completion of the write cycle.
Figure 8 illustrates the page write sequence.
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3, Bit 4 and Bit 7 of the
status register can be written using the write status
register instruction. Figure 7 illustrates the sequence of
writing to status register.
enable latch will not have been properly set. Also, for a
successful write operation the address of the memory
location(s) to be programmed must be outside the pro-
tected address field.
Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the
CS low,
issuing a write instruction via the SI line, followed by the
16-bit address for 25C09/17. (only 10-bit addresses are
used for 25C09, 11-bit addresses are used for 25C17.
The rest of the bits are don't care bits) and 8-bit address
for 25C11/03/05 (for the 25C05, bit 3 of the read data
instruction contains address A8). Programming will start
after the
CS is brought high. Figure 6 illustrates byte write
sequence.
Page Write
The CAT25C11/03/05/09/17 features page write capa-
bility. After the initial byte, the host may continue to write
after the WREN instruction to enable writes to thee
Figure 5. RDSR Instruction Timing
0
1
2
3
45
67
8
10
911
12
13
14
SCK
SI
DATA OUT
MSB
HIGH IMPEDANCE
OPCODE
SO
7
6
5
4
3
2
1
0
CS
00
0
00
1
0
1
Note: Dashed Line= mode (1, 1) – – – –




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