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HX711 Datasheet(PDF) 4 Page - Avia Semiconductor Co., Ltd. |
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HX711 Datasheet(HTML) 4 Page - Avia Semiconductor Co., Ltd. |
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4 / 9 page  HX711 AVIA SEMICONDUCTOR V2.0 4 Analog Inputs Channel A differential input is designed to interface directly with a bridge sensor’s differential output. It can be programmed with a gain of 128 or 64. The large gains are needed to accommodate the small output signal from the sensor. When 5V supply is used at the AVDD pin, these gains correspond to a full-scale differential input voltage of ±20mV or ±40mV respectively. Channel B differential input has a fixed gain of 32. The full-scale input voltage range is ±80mV, when 5V supply is used at the AVDD pin. Power Supply Options Digital power supply (DVDD) should be the same power supply as the MCU power supply. When using internal analog supply regulator, the dropout voltage of the regulator depends on the external transistor used. The output voltage is equal to VAVDD=VBG*(R1+R2)/R2 (Fig.1). This voltage should be designed with a minimum of 100mV below VSUP voltage. If the on-chip analog supply regulator is not used, the VSUP pin should be connected to either AVDD or DVDD, depending on which voltage is higher. Pin VFB should be connected to Ground and pin BASE becomes NC. The external 0.1uF bypass capacitor shown on Fig. 1 at the VBG output pin is then not needed. Clock Source Options By connecting pin XI to Ground, the on-chip oscillator is activated. The nominal output data rate when using the internal oscillator is 10 (RATE=0) or 80SPS (RATE=1). If accurate output data rate is needed, crystal or external reference clock can be used. A crystal can be directly connected across XI and XO pins. An external clock can be connected to XI pin, through a 20pF ac coupled capacitor. This external clock is not required to be a square wave. It can come directly from the crystal output pin of the MCU chip, with amplitude as low as 150 mV. When using a crystal or an external clock, the internal oscillator is automatically powered down. Output Data Rate and Format When using the on-chip oscillator, output data rate is typically 10 (RATE=0) or 80SPS (RATE=1). When using external clock or crystal, output data rate is directly proportional to the clock or crystal frequency. Using 11.0592MHz clock or crystal results in an accurate 10 (RTE=0) or 80SPS (RATE=1) output data rate. The output 24 bits of data is in 2’s complement format. When input differential signal goes out of the 24-bit range, the output data will be saturated at 800000h (MIN) or 7FFFFFh (MAX), until the input signal comes back to the input range. Serial Interface Pin PD_SCK and DOUT are used for data retrieval, input selection, gain selection and power down controls. When output data is not ready for retrieval, digital output pin DOUT is high. Serial clock input PD_SCK should be low. When DOUT goes to low, it indicates data is ready for retrieval. By applying 25~27 positive clock pulses at the PD_SCK pin, data is shifted out from the DOUT output pin. Each PD_SCK pulse shifts out one bit, starting with the MSB bit first, until all 24 bits are shifted out. The 25 th pulse at PD_SCK input will pull DOUT pin back to high (Fig.2). Input and gain selection are controlled by the number of the input PD_SCK pulses (Table 3). PD_SCK clock pulses should not be less than 25 or more than 27 within one conversion period, to avoid causing serial communication error. PD_SCK Pulses Input channel Gain 25 A 128 26 B 32 27 A 64 Table 3 Input Channel and Gain Selection |
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