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GD25Q80CEEG Datasheet(PDF) 22 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25Q80CEEG Datasheet(HTML) 22 Page - GigaDevice Semiconductor (Beijing) Inc. |
22 / 67 page 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q80C 22 7.11. Quad I/O Fast Read (EBH) The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the 3-Byte address (A23- 0) and a “Continuous Read Mode” Byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO2, IO3, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in followed Figure 11. The first Byte addressed can be at any location. The address is automatically incremented to the next higher address after each Byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command. Quad I/O Fast Read with “Continuous Read Mode” The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-Byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The command sequence is shown in followed Figure 12 . If the “Continuous Read Mode” bits (M7-0) are any value other than AXH, the next command requires the first EBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M7-0) before issuing normal command. Figure 11. Quad I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH) Figure 12. Quad I/O Fast Read Sequence Diagram (M7-0= AXH) Command 0 1 2 3 4 5 6 7 EBH CS# SCLK SI(IO0) SO(IO1) 8 9 10 11 12 13 14 15 4 0 4 0 4 0 4 0 16 17 18 19 20 21 22 23 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 A23-16 A15-8 A7-0 M7-0 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 WP#(IO2) HOLD#(IO3) 4 5 6 7 Dummy Byte1 Byte2 0 1 2 3 4 5 6 7 CS# SCLK 8 9 10 11 12 13 14 15 SI(IO0) SO(IO1) WP#(IO2) HOLD#(IO3) 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 5 6 7 A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 |
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