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VSC8116 Datasheet(PDF) 5 Page - Vitesse Semiconductor Corporation

No. de Pieza. VSC8116
Descripción  ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation
Descarga  20 Pages
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Fabricante  VITESSE [Vitesse Semiconductor Corporation]
Página de inicio  http://www.vitesse.com
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VSC8116 Datasheet(HTML) 5 Page - Vitesse Semiconductor Corporation

 
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G52220-0, Rev 4.1
© VITESSE SEMICONDUCTOR CORPORATION
Page 5
1/8/00
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8116
ATM/SONET/SDH 622/155Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Figure 4: Equipment Loopback Data Path
Split Loopback
Equipment and facility loopback modes can be enabled simultaneously. See descriptions for equipment and
facility loop modes above. The only change is, since they are both active, RXDATAIN will not be deserialized
and presented to RXOUT[0:7], and TXIN[0:7] will not be serialized and present to TXDATAOUT.
Figure 5: Split Loopback Datapath
Loop Timing
LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted high. In this mode the CMU
is bypassed by using the receive clock (RXCLKIN), and the entire part is synchronously clocked from a single
external source.
DQ
D
Q
1:8
Serial to
Parallel
Q
D
RXDATAIN
TXDATAOUT
RXOUT[7:0]
Q
D
8:1
Parallel to
Serial
TXIN[7:0]
÷ 8
PLL
÷ 8
RXLSCKOUT
TXLSCKOUT
0
1
EQULOOP
0
1
RXCLKIN
D
Q
1:8
Serial to
Parallel
RXOUT[7:0]
Q
D
8:1
Parallel to
Serial
TXIN[7:0]
RXLSCKOUT
DQ
Q
D
RXDATAIN
TXDATAOUT
0
1
FACLOOP
RXCLKIN
0
1
÷ 8
PLL
0
1
EQULOOP
0
1


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