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93LC66BTEP Datasheet(PDF) 7 Page - Microchip Technology

No. de Pieza. 93LC66BTEP
Descripción  4K Microwire Compatible Serial EEPROM
Descarga  24 Pages
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Fabricante  MICROCHIP [Microchip Technology]
Página de inicio  http://www.microchip.com
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93LC66BTEP Datasheet(HTML) 7 Page - Microchip Technology

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 2003 Microchip Technology Inc.
DS21795B-page 7
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.5
ERASE ALL (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle is
identical to the ERASE cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL).
Note:
Issuing a Start bit and then taking CS low
will clear the READY/BUSY status from
DO.
VCC must be
≥ 4.5V for proper operation of ERAL.
FIGURE 2-3:
ERAL TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-4:
ERAL TIMING FOR 93C DEVICES
CS
CLK
DI
DO
TCSL
CHECK STATUS
10
0
1
0
X
•••
X
TSV
TCZ
BUSY
READY
HIGH-Z
TEC
HIGH-Z
VCC must be
≥ 4.5V for proper operation of ERAL.
CS
CLK
DI
DO
TCSL
CHECK STATUS
10
0
1
0
X
•••
X
TSV
TCZ
BUSY
READY
HIGH-Z
TEC
HIGH-Z


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