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TPS40074 Datasheet(PDF) 8 Page - Texas Instruments |
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TPS40074 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 38 page www.ti.com APPLICATION INFORMATION MINIMUM PULSE WIDTH SLEW RATE LIMIT ON VDD 13 7 14 12 10 8 ILIM HDRV SW LDRV VDD PGND TPS40074 C R VIN UDG−05058 +_ TPS40074 SLUS617–APRIL 2005 The TPS40074 allows the user to construct synchronous voltage mode buck converters with inputs ranging from 4.5 V to 28 V and outputs as low as 700 mV. Predictive gate drive circuitry optimizes switching delays for increased efficiency and improved converter output power capability. Voltage feed-forward is employed to ease loop compensation for wide input range designs and provide better line transient response. An on-board unity gain differential amplifier is provided for remote sensing in applications that require the tightest load regulation. The TPS40074 incorporates circuitry to allow startup into a pre-existing output voltage without sinking current from the source of the pre-existing output voltage. This avoids damaging sensitive loads at startup. The controller can be synchronized to an external clock source or can free run at a user programmable frequency. An integrated power good indicator is available for logic (open drain) output of the condition of the output of the converter. The TPS40074 has limitations on the minimum pulse width that can be used to design a converter. Reliable operation is guaranteed for nominal pulse widths of 150 ns and above. This places some restrictions on the conversion ratio that can be achieved at a given switching frequency. Figure 2 shows minimum output voltage for a given input voltage and frequency. The regulator that supplies power for the drivers on the TPS40074 requires a limited rising slew rate on VDD for proper operation if the input voltage is above 10 V. If the slew rate is too great, this regulator can over shoot and damage to the part can occur. To ensure that the part operates properly, limit the slew rate to no more than 0.12 V/µs as the voltage at VDD crosses 8 V. If necessary, an R-C filter can be used on the VDD pin of the device. Connect the resistor from the VDD pin to the input supply of the converter. Connect the capacitor from the VDD pin to PGND. There should not be excessive (more than a 200-mV) voltage drop across the resistor in normal operation. This places some constraints on the R-C values that can be used. Figure 1 is a schematic fragment that shows the connection of the R-C slew rate limit circuit. Equation 1 and Equation 2 give values for R and C that limits the slew rate in the worst case condition. Figure 1. Limiting the Slew Rate 8 |
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