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AM30LV0064D Datasheet(PDF) 4 Page - Advanced Micro Devices

No. de pieza AM30LV0064D
Descripción Electrónicos  64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology
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Fabricante Electrónico  AMD [Advanced Micro Devices]
Página de inicio  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM30LV0064D Datasheet(HTML) 4 Page - Advanced Micro Devices

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Am30LV0064D
GENERAL DESCRIPTION
The Am30LV0064D is a 64 Mbit mass storage Flash
memory device, organized as 8 Kbyte (+256 byte)
blocks (1,024 blocks total), each with 16 pages of 512
(+16) bytes (16,384 pages total).
The device is suited to high-density applications in
which data is sequential and requires frequent, fast
write capability. The UltraNAND™ block and page ar-
chitecture is capable of accommodating applications
requiring IDE disk drive-compatible blocks.
Each device requires only a single 3.0 volt power
supply for read, program, and erase functions. Inter-
nally generated and regulated voltages are provided
for program and erase operations. A VCCQ pin is pro-
vided to allow 5 volts to be applied to the output buffer
logic. With 5 volt tolerant inputs, the VCCQ pin provides
the Flash device with 5 volt tolerant I/O.
The Am30LV0064D is entirely command set compati-
ble with industry standard NAND instructions and
timing. Commands are written to the command regis-
ter through the 8-bit I/O bus using standard NAND
write timing. Register contents serve as inputs to an
internal state-machine that controls the read, erase,
and programming circuitry. Write cycles also internally
latch addresses and data needed for the read, program-
ming, and erase operations. Reading data out of the
device is similar to reading from NAND Flash devices. The
device has an initial page read access time of 7 µs, with
subsequent byte accesses of less than 50 ns per byte.
Device programming occurs on a page basis by exe-
cuting the Input Data and Program Data command
sequences. This initiates the Embedded Program al-
gorithm—an internal algorithm that automatically times
the program pulse widths and verifies proper cell margin.
Device erasure is performed on a block basis and occurs
by executing the Block Erase command sequence. This
initiates the Embedded Erase algorithm—an internal
algorithm that automatically executes the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin. The
block erase architecture allows memory blocks to be
erased and reprogrammed without affecting the data
contents of other blocks. The Erase Suspend/Erase
Resume feature enables the user to put erase on hold
for any period of time to read data from, or program
data to, any block that is not selected for erasure. True
background erase can thus be achieved. The device is
fully erased when shipped from the factory.
The host system can detect whether a sequential read,
program, or Block Erase operation is complete by ob-
serving the RY/BY# pin or by reading the status
register. After a program or erase cycle has been com-
pleted, the device is ready to accept another command.
Hardware data protection is provided by a write pro-
tect (WP#) input pin which inhibits all program and
erase operations when asserted (low).
The device offers a standby mode as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the high-
est levels of quality, reliability and cost effectiveness.


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