ADS5221

SBAS262A

3

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DIGITAL INPUTS

Logic Family

Convert Command

Start Conversion

100

µA

10

µA

High Level Input Voltage

+1.7

V

Low Level Input Voltage

+0.7

V

Input Capacitance

5pF

DIGITAL OUTPUTS

Logic Family

Logic Coding

VDRV = 2.5V

+0.1

V

+2.4

V

3-State Enable Time

OE = H

20

40

ns

3-State Disable Time

OE = L

2

10

ns

Output Capacitance

5pF

Unless Otherwise Noted)

Zero Error (referred to midscale)

±0.5

±1.5

%FS

Zero Error Drift (referred to midscale)

5

ppm/

°C

±0.4

%FS

38

ppm/

°C

Power-Supply Rejection of Gain

∆AV

56

dB

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1V)

±5

±35

mV

Load Regulation at 1.0mA

0.8

mV

Output Voltage Error (0.5V)

±2.5

mV

Load Regulation at 0.5mA

0.1

mV

POWER-SUPPLY REQUIREMENTS

Operating

+3.0

+3.3

+3.6

V

Driver Supply Voltage: VDRV

+2.3

+2.5

+3.6

V

Operating (External Reference)

86

mA

Power Dissipation: VDRV = 2.5V

285

295

mW

VDRV = 3.3V

290

mW

Standard Power-Down

15

mW

Quasi Power-Down

70

mW

Thermal Resistance,

θ

JA

TQFP-48

63.7

°C/W

QFN-48

26.1

°C/W

NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic.

(2) dBFS means dB relative to Full-Scale.

(3) 2-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the

2-tone fundamental envelope.

(4) Effective Number of Bits (ENOB) is defined by (SINAD – 1.76) /6.02.

(5) A 50k

Ω pull-down resistor is inserted internally on the OE pin.

(6) Includes internal reference.

ADS5221

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS-Compatible

Rising Edge of Convert Clock

CMOS-Compatible

Straight Offset Binary or BTC