74AUP1G126GW datasheet(1/20 Pages) PHILIPS

No. de pieza	74AUP1G126GW

Descripción Electrónicos	Low-Power buffer/line driver; 3-state

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Fabricante Electrónico	PHILIPS [NXP Semiconductors]

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1.

General description

The 74AUP1G126 is a high-performance, low-power, low-voltage, Si-gate CMOS device,

superior to most advanced CMOS compatible TTL families.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

VCC range from 0.8 V to 3.6 V.

This device is fully speciﬁed for partial Power-down applications using IOFF.

The IOFF circuitry disables the output, preventing the damaging backﬂow current through

the device when it is powered down.

The 74AUP1G126 provides the single non-inverting buffer/line driver with 3-state output.

The 3-state output is controlled by the output enable input (OE). A LOW level at pin OE

causes the output to assume a high-impedance OFF-state.

This device has the input-disable feature, which allows ﬂoating input signals. The inputs

are disabled when the output enable input OE is LOW.

2.

Features

s Wide supply voltage range from 0.8 V to 3.6 V

s High noise immunity

s Complies with JEDEC standards:

x JESD8-12 (0.8 V to 1.3 V)

x JESD8-11 (0.9 V to 1.65 V)

x JESD8-7 (1.2 V to 1.95 V)

x JESD8-5 (1.8 V to 2.7 V)

x JESD8-B (2.7 V to 3.6 V)

s ESD protection:

x HBM JESD22-A114-C exceeds 2000 V

x MM JESD22-A115-A exceeds 200 V

x CDM JESD22-C101-C exceeds 1000 V

s Low static power consumption; ICC = 0.9 µA (maximum)

s Latch-up performance exceeds 100 mA per JESD 78 Class II

s Inputs accept voltages up to 3.6 V

s Low noise overshoot and undershoot < 10 % of VCC

s Input-disable feature allows ﬂoating input conditions

74AUP1G126

Low-power buffer/line driver; 3-state

Rev. 01 — 25 July 2005

Product data sheet

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74AUP1G126GW Datasheet(PDF) 1 Page - NXP Semiconductors

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