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93LC66CXESTG Datasheet(PDF) 11 Page - Microchip Technology

No. de Pieza. 93LC66CXESTG
Descripción  4K Microwire Compatible Serial EEPROM
Descarga  24 Pages
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Fabricante  MICROCHIP [Microchip Technology]
Página de inicio  http://www.microchip.com
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93LC66CXESTG Datasheet(HTML) 11 Page - Microchip Technology

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 2003 Microchip Technology Inc.
DS21795B-page 11
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
3.0
PIN DESCRIPTIONS
TABLE 3-1:
PIN DESCRIPTIONS
3.1
Chip Select (CS)
A high level selects the device; a low level deselects
the device and forces it into Standby mode. However, a
programming cycle which is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into Standby mode as soon as the
programming cycle is completed.
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal
control logic is held in a Reset status.
3.2
Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93XX series
device. Opcodes, address and data bits are clocked in
on the positive edge of CLK. Data bits are also clocked
out on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing opcode, address and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but the Start condition has not been
detected (DI = 0), any number of clock cycles can be
received by the device without changing its status (i.e.,
waiting for a Start condition).
CLK cycles are not required during the self-timed Write
(i.e., auto ERASE/WRITE) cycle.
After detection of a Start condition the specified number
of clock cycles (respectively low-to-high transitions of
CLK) must be provided. These clock cycles are
required to clock in all required opcode, address and
data bits before an instruction is executed. CLK and DI
then become don't care inputs waiting for a new Start
condition to be detected.
3.3
Data In (DI)
Data In (DI) is used to clock in a Start bit, opcode,
address and data synchronously with the CLK input.
3.4
Data Out (DO)
Data Out (DO) is used in the READ mode to output
data synchronously with the CLK input (TPD after the
positive edge of CLK).
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought high after being low for minimum Chip Select
low time (TCSL) and an Erase or Write operation has
been initiated.
The Status signal is not available on DO, if CS is held
low during the entire ERASE or WRITE cycle. In this
case, DO is in the HIGH-Z mode. If status is checked
after the ERASE/WRITE cycle, the data line will be high
to indicate the device is ready.
Note:
Issuing a Start bit and then taking CS low
will clear the READY/BUSY status from
DO.
3.5
Organization (ORG)
When the ORG pin is connected to VCC or Logic HI, the
(x16) memory organization is selected. When the ORG
pin is tied to VSS or Logic LO, the (x8) memory
organization is selected. For proper operation, ORG
must be tied to a valid logic level.
93XX66A devices are always x8 organization and
93XX66B devices are always x16 organization.
Name
SOIC/PDIP/
MSOP/TSSOP
SOT-23
Rotated SOIC
Function
CS
1
5
3
Chip Select
CLK
2
4
4
Serial Clock
DI
3
3
5
Data In
DO
4
1
6
Data Out
VSS
52
7
Ground
ORG/NC
6
N/A
8
Organization / 93XX66C
No Internal Connection / 93XX66A/B
NC
7
N/A
1
No Internal Connection
VCC
8
6
2
Power Supply


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